1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s 2 3; Generate REG_SEQUENCE instead of combine 4; CHECK-NOT: combine(#0 5 6; Function Attrs: nounwind 7define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, ptr nocapture %a2, ptr nocapture readonly %a3, i32 %a4) #0 { 8b0: 9 %v0 = lshr i32 %a4, 1 10 %v1 = icmp eq i32 %v0, 0 11 br i1 %v1, label %b3, label %b1 12 13b1: ; preds = %b0 14 br label %b2 15 16b2: ; preds = %b2, %b1 17 %v5 = phi i32 [ 0, %b1 ], [ %v71, %b2 ] 18 %v6 = phi ptr [ %a0, %b1 ], [ %v9, %b2 ] 19 %v7 = phi ptr [ %a1, %b1 ], [ %v11, %b2 ] 20 %v8 = phi ptr [ %a2, %b1 ], [ %v70, %b2 ] 21 %v9 = getelementptr inbounds i64, ptr %v6, i32 1 22 %v10 = load i64, ptr %v6, align 8, !tbaa !0 23 %v11 = getelementptr inbounds i64, ptr %v7, i32 1 24 %v12 = load i64, ptr %v7, align 8, !tbaa !0 25 %v13 = trunc i64 %v10 to i32 26 %v14 = lshr i64 %v10, 32 27 %v15 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v13) 28 %v16 = trunc i64 %v12 to i32 29 %v17 = lshr i64 %v12, 32 30 %v18 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v16) 31 %v19 = trunc i64 %v15 to i32 32 %v20 = lshr i64 %v15, 32 33 %v21 = getelementptr inbounds i16, ptr %a3, i32 %v19 34 %v22 = load i16, ptr %v21, align 2, !tbaa !3 35 %v23 = trunc i64 %v20 to i32 36 %v24 = getelementptr inbounds i16, ptr %a3, i32 %v23 37 %v25 = load i16, ptr %v24, align 2, !tbaa !3 38 %v26 = trunc i64 %v18 to i32 39 %v27 = lshr i64 %v18, 32 40 %v28 = getelementptr inbounds i16, ptr %a3, i32 %v26 41 %v29 = load i16, ptr %v28, align 2, !tbaa !3 42 %v30 = trunc i64 %v27 to i32 43 %v31 = getelementptr inbounds i16, ptr %a3, i32 %v30 44 %v32 = load i16, ptr %v31, align 2, !tbaa !3 45 %v33 = zext i16 %v32 to i64 46 %v34 = shl nuw nsw i64 %v33, 32 47 %v35 = zext i16 %v29 to i64 48 %v36 = or i64 %v35, %v34 49 %v37 = zext i16 %v25 to i64 50 %v38 = shl nuw nsw i64 %v37, 32 51 %v39 = zext i16 %v22 to i64 52 %v40 = or i64 %v39, %v38 53 %v41 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v36, i64 %v40) 54 %v42 = getelementptr inbounds i64, ptr %v8, i32 1 55 store i64 %v41, ptr %v8, align 8, !tbaa !0 56 %v43 = trunc i64 %v14 to i32 57 %v44 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v43) 58 %v45 = trunc i64 %v17 to i32 59 %v46 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v45) 60 %v47 = trunc i64 %v44 to i32 61 %v48 = lshr i64 %v44, 32 62 %v49 = getelementptr inbounds i16, ptr %a3, i32 %v47 63 %v50 = load i16, ptr %v49, align 2, !tbaa !3 64 %v51 = trunc i64 %v48 to i32 65 %v52 = getelementptr inbounds i16, ptr %a3, i32 %v51 66 %v53 = load i16, ptr %v52, align 2, !tbaa !3 67 %v54 = trunc i64 %v46 to i32 68 %v55 = lshr i64 %v46, 32 69 %v56 = getelementptr inbounds i16, ptr %a3, i32 %v54 70 %v57 = load i16, ptr %v56, align 2, !tbaa !3 71 %v58 = trunc i64 %v55 to i32 72 %v59 = getelementptr inbounds i16, ptr %a3, i32 %v58 73 %v60 = load i16, ptr %v59, align 2, !tbaa !3 74 %v61 = zext i16 %v60 to i64 75 %v62 = shl nuw nsw i64 %v61, 32 76 %v63 = zext i16 %v57 to i64 77 %v64 = or i64 %v63, %v62 78 %v65 = zext i16 %v53 to i64 79 %v66 = shl nuw nsw i64 %v65, 32 80 %v67 = zext i16 %v50 to i64 81 %v68 = or i64 %v67, %v66 82 %v69 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v64, i64 %v68) 83 %v70 = getelementptr inbounds i64, ptr %v8, i32 2 84 store i64 %v69, ptr %v42, align 8, !tbaa !0 85 %v71 = add nsw i32 %v5, 1 86 %v72 = icmp ult i32 %v71, %v0 87 br i1 %v72, label %b2, label %b3 88 89b3: ; preds = %b2, %b0 90 ret void 91} 92 93; Function Attrs: nounwind readnone 94declare i64 @llvm.hexagon.S2.vzxthw(i32) #1 95 96; Function Attrs: nounwind readnone 97declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64) #1 98 99attributes #0 = { nounwind "target-cpu"="hexagonv60" } 100attributes #1 = { nounwind readnone } 101 102!0 = !{!1, !1, i64 0} 103!1 = !{!"omnipotent char", !2, i64 0} 104!2 = !{!"Simple C/C++ TBAA"} 105!3 = !{!4, !4, i64 0} 106!4 = !{!"short", !1, i64 0} 107