xref: /llvm-project/llvm/test/CodeGen/Hexagon/reg-eq-cmp.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; Generate reg = cmp.
3
4@g0 = common global i8 0, align 1
5@g1 = common global i32 0, align 4
6@g2 = common global i8 0, align 1
7@g3 = global i8 65, align 1
8
9; CHECK-LABEL: f0:
10; CHECK: r{{[0-9]+}} = cmp.eq(r{{[0-9]+}},#65)
11define i32 @f0() #0 {
12b0:
13  %v0 = load i8, ptr @g0, align 1, !tbaa !0
14  %v1 = icmp eq i8 %v0, 65
15  %v2 = zext i1 %v1 to i32
16  %v3 = load i32, ptr @g1, align 4, !tbaa !3
17  %v4 = or i32 %v2, %v3
18  store i32 %v4, ptr @g1, align 4, !tbaa !3
19  store i8 66, ptr @g2, align 1, !tbaa !0
20  ret i32 undef
21}
22
23; CHECK-LABEL: f1:
24; CHECK: r{{[0-9]+}} = cmp.eq(r{{[0-9]+}},r{{[0-9]+}})
25define i32 @f1() #0 {
26b0:
27  %v0 = load i8, ptr @g0, align 1, !tbaa !0
28  %v1 = load i8, ptr @g3, align 1, !tbaa !0
29  %v2 = icmp eq i8 %v0, %v1
30  %v3 = zext i1 %v2 to i32
31  %v4 = load i32, ptr @g1, align 4, !tbaa !3
32  %v5 = or i32 %v3, %v4
33  store i32 %v5, ptr @g1, align 4, !tbaa !3
34  store i8 66, ptr @g2, align 1, !tbaa !0
35  ret i32 undef
36}
37
38attributes #0 = { nounwind }
39
40!0 = !{!1, !1, i64 0}
41!1 = !{!"omnipotent char", !2}
42!2 = !{!"Simple C/C++ TBAA"}
43!3 = !{!4, !4, i64 0}
44!4 = !{!"int", !1}
45