xref: /llvm-project/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon -tail-dup-size=1 < %s | FileCheck %s
2
3target triple = "hexagon-unknown--elf"
4
5; Make sure we put the two conditionally executed adds in a packet.
6;     {
7;       p0 = cmp.gt(r2, r1)
8;       if (!p0.new) r0 = add(r2, r1)
9;       if (p0.new) r0 = add(r0, #10)
10;     }
11; CHECK: cmp
12; CHECK-NEXT: add
13; CHECK-NEXT: add
14define i32 @f0(i32 %a0, i32 %a1, i32 %a2) #0 {
15b0:
16  %v0 = icmp sgt i32 %a2, %a1
17  br i1 %v0, label %b1, label %b2
18
19b1:                                               ; preds = %b0
20  %v1 = add nsw i32 %a0, 10
21  br label %b3
22
23b2:                                               ; preds = %b0
24  %v2 = add nsw i32 %a2, %a1
25  br label %b3
26
27b3:                                               ; preds = %b2, %b1
28  %v3 = phi i32 [ %v1, %b1 ], [ %v2, %b2 ]
29  %v4 = add nsw i32 %v3, 1
30  ret i32 %v4
31}
32
33attributes #0 = { nounwind readnone "target-cpu"="hexagonv5" }
34