1; RUN: llc -mtriple=hexagon < %s | FileCheck %s 2; 3; Check that we generate new value stores in V60. 4 5; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}}) 6; CHECK: vmem(r{{[0-9]+}}+#{{[0-9]+}}) = v{{[0-9]+}}.new 7 8define void @f0(ptr nocapture readonly %a0, i32 %a1, ptr nocapture %a2) #0 { 9b0: 10 %v2 = load <16 x i32>, ptr %a0, align 64 11 %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v2, <16 x i32> undef, i32 %a1) 12 store <16 x i32> %v3, ptr %a2, align 64 13 ret void 14} 15 16; Function Attrs: nounwind readnone 17declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0 18 19attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 20