1; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s 2; 3; Expand-condsets eliminates the "mux" instruction, which is what this 4; testcase is checking. 5 6; Test that we don't generate a new value compare if the operands are 7; the same register. 8 9; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new,[[REG0]]) 10; CHECK: cmp.eq([[REG1:(r[0-9]+)]],[[REG1]]) 11 12%s.0 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [2 x i32], ptr, ptr, ptr, %s.1, ptr, [8 x i8], i8 } 13%s.1 = type { i32, i16, i16 } 14 15@g0 = external global %s.0 16@g1 = external unnamed_addr constant [23 x i8], align 8 17 18; Function Attrs: nounwind 19declare void @f0(ptr nocapture, ptr nocapture readonly, ...) #0 20 21define void @f1() #1 { 22b0: 23 %v0 = load ptr, ptr undef, align 4 24 %v1 = load i32, ptr undef, align 4 25 br i1 undef, label %b4, label %b1 26 27b1: ; preds = %b0 28 %v2 = icmp slt i32 %v1, 0 29 %v3 = lshr i32 %v1, 5 30 %v4 = add i32 %v3, -134217728 31 %v5 = select i1 %v2, i32 %v4, i32 %v3 32 %v6 = getelementptr inbounds i32, ptr %v0, i32 %v5 33 %v7 = icmp ult ptr %v6, %v0 34 %v8 = select i1 %v7, i32 0, i32 1 35 br i1 undef, label %b2, label %b4 36 37b2: ; preds = %b1 38 %v9 = icmp slt i32 %v1, 0 39 %v10 = lshr i32 %v1, 5 40 %v11 = add i32 %v10, -134217728 41 %v12 = select i1 %v9, i32 %v11, i32 %v10 42 %v13 = getelementptr inbounds i32, ptr %v0, i32 %v12 43 %v14 = icmp ult ptr %v13, %v0 44 %v15 = select i1 %v14, i32 0, i32 1 45 %v16 = icmp eq i32 %v8, %v15 46 br i1 %v16, label %b4, label %b3 47 48b3: ; preds = %b2 49 call void (ptr, ptr, ...) @f0(ptr @g0, ptr @g1, i32 %v8, i32 %v15) #0 50 unreachable 51 52b4: ; preds = %b2, %b1, %b0 53 br i1 undef, label %b6, label %b5 54 55b5: ; preds = %b4 56 unreachable 57 58b6: ; preds = %b4 59 ret void 60} 61 62attributes #0 = { nounwind "target-cpu"="hexagonv5" } 63attributes #1 = { "target-cpu"="hexagonv5" } 64