xref: /llvm-project/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=hexagon < %s | FileCheck %s
3
4define i64 @f0(ptr %a0, <8 x i8> %a1) #0 {
5; CHECK-LABEL: f0:
6; CHECK:       // %bb.0: // %b0
7; CHECK-NEXT:    {
8; CHECK-NEXT:     r0 = memub(r0+#0)
9; CHECK-NEXT:    }
10; CHECK-NEXT:    {
11; CHECK-NEXT:     r5:4 = combine(#0,#0)
12; CHECK-NEXT:    }
13; CHECK-NEXT:    {
14; CHECK-NEXT:     p0 = r0
15; CHECK-NEXT:    }
16; CHECK-NEXT:    {
17; CHECK-NEXT:     r1:0 = vmux(p0,r3:2,r5:4)
18; CHECK-NEXT:    }
19; CHECK-NEXT:    {
20; CHECK-NEXT:     jumpr r31
21; CHECK-NEXT:    }
22b0:
23  %v0 = load <8 x i1>, ptr %a0, align 1
24  %v1 = select <8 x i1> %v0, <8 x i8> %a1, <8 x i8> zeroinitializer
25  %v2 = bitcast <8 x i8> %v1 to i64
26  ret i64 %v2
27}
28
29define i32 @f1(ptr %a0, <4 x i8> %a1) #0 {
30; CHECK-LABEL: f1:
31; CHECK:       // %bb.0: // %b0
32; CHECK-NEXT:    {
33; CHECK-NEXT:     r0 = memub(r0+#0)
34; CHECK-NEXT:    }
35; CHECK-NEXT:    {
36; CHECK-NEXT:     r3:2 = combine(#0,#0)
37; CHECK-NEXT:    }
38; CHECK-NEXT:    {
39; CHECK-NEXT:     r5:4 = vzxtbh(r1)
40; CHECK-NEXT:    }
41; CHECK-NEXT:    {
42; CHECK-NEXT:     p0 = r0
43; CHECK-NEXT:    }
44; CHECK-NEXT:    {
45; CHECK-NEXT:     r1:0 = vmux(p0,r5:4,r3:2)
46; CHECK-NEXT:    }
47; CHECK-NEXT:    {
48; CHECK-NEXT:     r0 = vtrunehb(r1:0)
49; CHECK-NEXT:    }
50; CHECK-NEXT:    {
51; CHECK-NEXT:     jumpr r31
52; CHECK-NEXT:    }
53b0:
54  %v0 = load <4 x i1>, ptr %a0, align 1
55  %v1 = select <4 x i1> %v0, <4 x i8> %a1, <4 x i8> zeroinitializer
56  %v2 = bitcast <4 x i8> %v1 to i32
57  ret i32 %v2
58}
59
60define i16 @f2(ptr %a0, <2 x i8> %a1) #0 {
61; CHECK-LABEL: f2:
62; CHECK:       // %bb.0: // %b0
63; CHECK-NEXT:    {
64; CHECK-NEXT:     r0 = memub(r0+#0)
65; CHECK-NEXT:    }
66; CHECK-NEXT:    {
67; CHECK-NEXT:     p1 = tstbit(r0,#4)
68; CHECK-NEXT:    }
69; CHECK-NEXT:    {
70; CHECK-NEXT:     p0 = r0
71; CHECK-NEXT:    }
72; CHECK-NEXT:    {
73; CHECK-NEXT:     r1 = mux(p1,r3,#0)
74; CHECK-NEXT:    }
75; CHECK-NEXT:    {
76; CHECK-NEXT:     r0 = mux(p0,r2,#0)
77; CHECK-NEXT:    }
78; CHECK-NEXT:    {
79; CHECK-NEXT:     r0 = insert(r1,#24,#8)
80; CHECK-NEXT:    }
81; CHECK-NEXT:    {
82; CHECK-NEXT:     jumpr r31
83; CHECK-NEXT:    }
84b0:
85  %v0 = load <2 x i1>, ptr %a0, align 1
86  %v1 = select <2 x i1> %v0, <2 x i8> %a1, <2 x i8> zeroinitializer
87  %v2 = bitcast <2 x i8> %v1 to i16
88  ret i16 %v2
89}
90
91define i8 @f3(ptr %a0, <1 x i8> %a1) #0 {
92; CHECK-LABEL: f3:
93; CHECK:       // %bb.0: // %b0
94; CHECK-NEXT:    {
95; CHECK-NEXT:     r0 = memub(r0+#0)
96; CHECK-NEXT:    }
97; CHECK-NEXT:    {
98; CHECK-NEXT:     p0 = r0
99; CHECK-NEXT:    }
100; CHECK-NEXT:    {
101; CHECK-NEXT:     r0 = mux(p0,r1,#0)
102; CHECK-NEXT:    }
103; CHECK-NEXT:    {
104; CHECK-NEXT:     jumpr r31
105; CHECK-NEXT:    }
106b0:
107  %v0 = load <1 x i1>, ptr %a0, align 1
108  %v1 = select <1 x i1> %v0, <1 x i8> %a1, <1 x i8> zeroinitializer
109  %v2 = bitcast <1 x i8> %v1 to i8
110  ret i8 %v2
111}
112
113define void @f4(ptr %a0, i64 %a1) #0 {
114; CHECK-LABEL: f4:
115; CHECK:       // %bb.0: // %b0
116; CHECK-NEXT:    {
117; CHECK-NEXT:     r5:4 = combine(#0,#0)
118; CHECK-NEXT:    }
119; CHECK-NEXT:    {
120; CHECK-NEXT:     p0 = vcmpb.eq(r3:2,r5:4)
121; CHECK-NEXT:    }
122; CHECK-NEXT:    {
123; CHECK-NEXT:     p0 = not(p0)
124; CHECK-NEXT:    }
125; CHECK-NEXT:    {
126; CHECK-NEXT:     r1 = p0
127; CHECK-NEXT:    }
128; CHECK-NEXT:    {
129; CHECK-NEXT:     memb(r0+#0) = r1
130; CHECK-NEXT:    }
131; CHECK-NEXT:    {
132; CHECK-NEXT:     jumpr r31
133; CHECK-NEXT:    }
134b0:
135  %v0 = bitcast i64 %a1 to <8 x i8>
136  %v1 = icmp ne <8 x i8> %v0, zeroinitializer
137  store <8 x i1> %v1, ptr %a0, align 1
138  ret void
139}
140
141define void @f5(ptr %a0, i32 %a1) #0 {
142; CHECK-LABEL: f5:
143; CHECK:       // %bb.0: // %b0
144; CHECK-NEXT:    {
145; CHECK-NEXT:     r3:2 = vsxtbh(r1)
146; CHECK-NEXT:    }
147; CHECK-NEXT:    {
148; CHECK-NEXT:     r5:4 = combine(#0,#0)
149; CHECK-NEXT:    }
150; CHECK-NEXT:    {
151; CHECK-NEXT:     p0 = vcmph.eq(r3:2,r5:4)
152; CHECK-NEXT:    }
153; CHECK-NEXT:    {
154; CHECK-NEXT:     p0 = not(p0)
155; CHECK-NEXT:    }
156; CHECK-NEXT:    {
157; CHECK-NEXT:     r2 = p0
158; CHECK-NEXT:    }
159; CHECK-NEXT:    {
160; CHECK-NEXT:     memb(r0+#0) = r2
161; CHECK-NEXT:    }
162; CHECK-NEXT:    {
163; CHECK-NEXT:     jumpr r31
164; CHECK-NEXT:    }
165b0:
166  %v0 = bitcast i32 %a1 to <4 x i8>
167  %v1 = icmp ne <4 x i8> %v0, zeroinitializer
168  store <4 x i1> %v1, ptr %a0, align 1
169  ret void
170}
171
172define void @f6(ptr %a0, i16 %a1) #0 {
173; CHECK-LABEL: f6:
174; CHECK:       // %bb.0: // %b0
175; CHECK-NEXT:    {
176; CHECK-NEXT:     r2 = extractu(r1,#8,#8)
177; CHECK-NEXT:    }
178; CHECK-NEXT:    {
179; CHECK-NEXT:     r3 = #255
180; CHECK-NEXT:    }
181; CHECK-NEXT:    {
182; CHECK-NEXT:     p1 = !bitsclr(r1,r3)
183; CHECK-NEXT:    }
184; CHECK-NEXT:    {
185; CHECK-NEXT:     p0 = cmp.eq(r2,#0)
186; CHECK-NEXT:    }
187; CHECK-NEXT:    {
188; CHECK-NEXT:     if (p0) r2 = #0
189; CHECK-NEXT:    }
190; CHECK-NEXT:    {
191; CHECK-NEXT:     r1 = mux(p1,#8,#0)
192; CHECK-NEXT:    }
193; CHECK-NEXT:    {
194; CHECK-NEXT:     r3 = mux(p1,#2,#0)
195; CHECK-NEXT:    }
196; CHECK-NEXT:    {
197; CHECK-NEXT:     r5 = setbit(r1,#2)
198; CHECK-NEXT:    }
199; CHECK-NEXT:    {
200; CHECK-NEXT:     r6 = setbit(r3,#0)
201; CHECK-NEXT:    }
202; CHECK-NEXT:    {
203; CHECK-NEXT:     if (!p0) r2 = #128
204; CHECK-NEXT:    }
205; CHECK-NEXT:    {
206; CHECK-NEXT:     r4 = mux(p0,#0,#32)
207; CHECK-NEXT:    }
208; CHECK-NEXT:    {
209; CHECK-NEXT:     if (!p1) r5 = add(r1,#0)
210; CHECK-NEXT:    }
211; CHECK-NEXT:    {
212; CHECK-NEXT:     if (!p1) r6 = add(r3,#0)
213; CHECK-NEXT:    }
214; CHECK-NEXT:    {
215; CHECK-NEXT:     r1 = setbit(r2,#6)
216; CHECK-NEXT:    }
217; CHECK-NEXT:    {
218; CHECK-NEXT:     r3 = setbit(r4,#4)
219; CHECK-NEXT:    }
220; CHECK-NEXT:    {
221; CHECK-NEXT:     r5 = or(r6,r5)
222; CHECK-NEXT:    }
223; CHECK-NEXT:    {
224; CHECK-NEXT:     if (!p0) r2 = add(r1,#0)
225; CHECK-NEXT:    }
226; CHECK-NEXT:    {
227; CHECK-NEXT:     if (!p0) r4 = add(r3,#0)
228; CHECK-NEXT:    }
229; CHECK-NEXT:    {
230; CHECK-NEXT:     r5 |= or(r4,r2)
231; CHECK-NEXT:    }
232; CHECK-NEXT:    {
233; CHECK-NEXT:     memb(r0+#0) = r5
234; CHECK-NEXT:    }
235; CHECK-NEXT:    {
236; CHECK-NEXT:     jumpr r31
237; CHECK-NEXT:    }
238b0:
239  %v0 = bitcast i16 %a1 to <2 x i8>
240  %v1 = icmp ne <2 x i8> %v0, zeroinitializer
241  store <2 x i1> %v1, ptr %a0, align 1
242  ret void
243}
244
245define void @f7(ptr %a0, i8 %a1) #0 {
246; CHECK-LABEL: f7:
247; CHECK:       // %bb.0: // %b0
248; CHECK-NEXT:    {
249; CHECK-NEXT:     r2 = #255
250; CHECK-NEXT:    }
251; CHECK-NEXT:    {
252; CHECK-NEXT:     p0 = !bitsclr(r1,r2)
253; CHECK-NEXT:    }
254; CHECK-NEXT:    {
255; CHECK-NEXT:     r1 = mux(p0,#1,#0)
256; CHECK-NEXT:    }
257; CHECK-NEXT:    {
258; CHECK-NEXT:     memb(r0+#0) = r1
259; CHECK-NEXT:    }
260; CHECK-NEXT:    {
261; CHECK-NEXT:     jumpr r31
262; CHECK-NEXT:    }
263b0:
264  %v0 = bitcast i8 %a1 to <1 x i8>
265  %v1 = icmp ne <1 x i8> %v0, zeroinitializer
266  store <1 x i1> %v1, ptr %a0, align 1
267  ret void
268}
269
270attributes #0 = { nounwind "target-features"="-packets" }
271