xref: /llvm-project/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; REQUIRES: asserts
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4; Make sure we can handle the 'q' constraint in the 128-byte mode.
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6target triple = "hexagon"
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8; CHECK-LABEL: fred
9; CHECK: if (q{{[0-3]}}) vmem
10define void @fred() #0 {
11  tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<128 x i1> undef, ptr undef, <32 x i32> undef) #0
12  ret void
13}
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15attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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