xref: /llvm-project/llvm/test/CodeGen/Hexagon/i16_VarArg.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; CHECK: dfcmp
3
4@g0 = internal constant [12 x i8] c"a < b = %d\0A\00"
5@g1 = internal constant [13 x i8] c"a <= b = %d\0A\00"
6@g2 = internal constant [12 x i8] c"a > b = %d\0A\00"
7@g3 = internal constant [13 x i8] c"a >= b = %d\0A\00"
8@g4 = internal constant [13 x i8] c"a == b = %d\0A\00"
9@g5 = internal constant [13 x i8] c"a != b = %d\0A\00"
10@g6 = global double 2.000000e+00
11@g7 = global double 5.000000e+00
12
13declare i32 @f0(ptr, ...) #0
14
15define i32 @f1() #0 {
16b0:
17  %v0 = load double, ptr @g6
18  %v1 = load double, ptr @g7
19  %v2 = fcmp olt double %v0, %v1
20  %v3 = fcmp ole double %v0, %v1
21  %v4 = fcmp ogt double %v0, %v1
22  %v5 = fcmp oge double %v0, %v1
23  %v6 = fcmp oeq double %v0, %v1
24  %v7 = fcmp une double %v0, %v1
25  %v8 = zext i1 %v2 to i16
26  %v15 = call i32 (ptr, ...) @f0(ptr @g0, i16 %v8)
27  ret i32 0
28}
29
30attributes #0 = { nounwind "target-cpu"="hexagonv5" }
31