1; RUN: llc -mtriple=hexagon < %s | FileCheck %s 2 3; Test that V_vzero and W_vzero intrinsics work. The W_vzero intrinsic was added 4; for v65/hvx. 5 6; CHECK-LABEL: f0: 7; CHECK: [[VREG1:v([0-9]+)]] = vxor([[VREG1]],[[VREG1]]) 8define void @f0(ptr nocapture %a0) #0 { 9b0: 10 %v1 = tail call <32 x i32> @llvm.hexagon.V6.vd0.128B() 11 store <32 x i32> %v1, ptr %a0, align 64 12 ret void 13} 14 15; Function Attrs: nounwind readnone 16declare <32 x i32> @llvm.hexagon.V6.vd0.128B() #1 17 18; CHECK-LABEL: f1: 19; CHECK: [[VREG2:v([0-9]+):([0-9]+).w]] = vsub([[VREG2]],[[VREG2]]) 20define void @f1(ptr nocapture %a0) #0 { 21b0: 22 %v1 = tail call <64 x i32> @llvm.hexagon.V6.vdd0.128B() 23 store <64 x i32> %v1, ptr %a0, align 128 24 ret void 25} 26 27; Function Attrs: nounwind readnone 28declare <64 x i32> @llvm.hexagon.V6.vdd0.128B() #1 29 30attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length128b" } 31attributes #1 = { nounwind readnone } 32