1; RUN: llc -mtriple=hexagon < %s | FileCheck %s 2; Check that we generate store instructions with global + offset 3 4%s.0 = type { i8, i8, i16, i32 } 5 6@g0 = common global %s.0 zeroinitializer, align 4 7 8; CHECK-LABEL: f0: 9; CHECK: memb(##g0+1) = r{{[0-9]+}} 10define void @f0(i32 %a0, i32 %a1, i8 zeroext %a2) #0 { 11b0: 12 %v0 = icmp sgt i32 %a0, %a1 13 br i1 %v0, label %b1, label %b2 14 15b1: ; preds = %b0 16 store i8 %a2, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 1 17 br label %b2 18 19b2: ; preds = %b1, %b0 20 ret void 21} 22 23; CHECK-LABEL: f1: 24; CHECK: memh(##g0+2) = r{{[0-9]+}} 25define void @f1(i32 %a0, i32 %a1, i16 signext %a2) #0 { 26b0: 27 %v0 = icmp sgt i32 %a0, %a1 28 br i1 %v0, label %b1, label %b2 29 30b1: ; preds = %b0 31 store i16 %a2, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 2), align 2 32 br label %b2 33 34b2: ; preds = %b1, %b0 35 ret void 36} 37 38attributes #0 = { nounwind "target-cpu"="hexagonv5" } 39