xref: /llvm-project/llvm/test/CodeGen/Hexagon/funnel-shift.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2
3; CHECK-LABEL: f0:
4; CHECK: r[[R00:[0-9]+]]:[[R01:[0-9]+]] = combine(r0,r1)
5; CHECK: r[[R02:[0-9]+]]:[[R03:[0-9]+]] = asl(r[[R00]]:[[R01]],#17)
6define i32 @f0(i32 %a0, i32 %a1) #1 {
7b0:
8  %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 17)
9  ret i32 %v0
10}
11
12; CHECK-LABEL: f1:
13; CHECK: r[[R10:[0-9]+]]:[[R11:[0-9]+]] = combine(r0,r1)
14; CHECK: r[[R12:[0-9]+]]:[[R13:[0-9]+]] = asl(r[[R10]]:[[R11]],r2)
15define i32 @f1(i32 %a0, i32 %a1, i32 %a2) #1 {
16b0:
17  %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 %a2)
18  ret i32 %v0
19}
20
21; CHECK-LABEL: f2:
22; CHECK: r[[R20:[0-9]+]]:[[R21:[0-9]+]] = asl(r1:0,#17)
23; CHECK: r[[R20]]:[[R21]] |= lsr(r3:2,#47)
24define i64 @f2(i64 %a0, i64 %a1) #1 {
25b0:
26  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 17)
27  ret i64 %v0
28}
29
30; CHECK-LABEL: f3:
31; CHECK: r[[R30:[0-9]+]]:[[R31:[0-9]+]] = asl(r1:0,r4)
32; CHECK: r[[R32:[0-9]+]] = sub(#64,r4)
33; CHECK: r[[R30]]:[[R31]] |= lsr(r3:2,r[[R32]])
34define i64 @f3(i64 %a0, i64 %a1, i64 %a2) #1 {
35b0:
36  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 %a2)
37  ret i64 %v0
38}
39
40; CHECK-LABEL: f4:
41; CHECK: r[[R40:[0-9]+]]:[[R41:[0-9]+]] = combine(r0,r1)
42; CHECK: r[[R42:[0-9]+]]:[[R43:[0-9]+]] = lsr(r[[R40]]:[[R41]],#17)
43define i32 @f4(i32 %a0, i32 %a1) #1 {
44b0:
45  %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 17)
46  ret i32 %v0
47}
48
49; CHECK-LABEL: f5:
50; CHECK: r[[R50:[0-9]+]]:[[R51:[0-9]+]] = combine(r0,r1)
51; CHECK: r[[R52:[0-9]+]]:[[R53:[0-9]+]] = lsr(r[[R50]]:[[R51]],r2)
52define i32 @f5(i32 %a0, i32 %a1, i32 %a2) #1 {
53b0:
54  %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 %a2)
55  ret i32 %v0
56}
57
58; CHECK-LABEL: f6:
59; CHECK: r[[R60:[0-9]+]]:[[R61:[0-9]+]] = lsr(r3:2,#17)
60; CHECK: r[[R60]]:[[R61]] |= asl(r1:0,#47)
61define i64 @f6(i64 %a0, i64 %a1) #1 {
62b0:
63  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 17)
64  ret i64 %v0
65}
66
67; CHECK-LABEL: f7:
68; CHECK: r[[R70:[0-9]+]]:[[R71:[0-9]+]] = lsr(r3:2,r4)
69; CHECK: r[[R72:[0-9]+]] = sub(#64,r4)
70; CHECK: r[[R70]]:[[R71]] |= asl(r1:0,r6)
71define i64 @f7(i64 %a0, i64 %a1, i64 %a2) #1 {
72b0:
73  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 %a2)
74  ret i64 %v0
75}
76
77; CHECK-LABEL: f8:
78; CHECK: r[[R80:[0-9]+]] = rol(r0,#17)
79define i32 @f8(i32 %a0) #1 {
80b0:
81  %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a0, i32 17)
82  ret i32 %v0
83}
84
85; CHECK-LABEL: f9:
86; CHECK: r[[R90:[0-9]+]]:[[R91:[0-9]+]] = combine(r0,r0)
87; CHECK: r[[R92:[0-9]+]]:[[R93:[0-9]+]] = asl(r[[R90]]:[[R91]],r1)
88define i32 @f9(i32 %a0, i32 %a1) #1 {
89b0:
90  %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a0, i32 %a1)
91  ret i32 %v0
92}
93
94; CHECK-LABEL: f10:
95; CHECK: r[[RA0:[0-9]+]]:[[RA1:[0-9]+]] = rol(r1:0,#17)
96define i64 @f10(i64 %a0, i64 %a1) #1 {
97b0:
98  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a0, i64 17)
99  ret i64 %v0
100}
101
102; CHECK-LABEL: f11:
103; CHECK: r[[RB0:[0-9]+]]:[[RB1:[0-9]+]] = asl(r1:0,r2)
104; CHECK: r[[RB2:[0-9]+]] = sub(#64,r2)
105; CHECK: r[[RB0]]:[[RB1]] |= lsr(r1:0,r[[RB2]])
106define i64 @f11(i64 %a0, i64 %a1) #1 {
107b0:
108  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a0, i64 %a1)
109  ret i64 %v0
110}
111
112; CHECK-LABEL: f12:
113; CHECK: r[[RC0:[0-9]+]] = rol(r0,#15)
114define i32 @f12(i32 %a0, i32 %a1) #1 {
115b0:
116  %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a0, i32 17)
117  ret i32 %v0
118}
119
120; CHECK-LABEL: f13:
121; CHECK: r[[RD0:[0-9]+]]:[[RD1:[0-9]+]] = combine(r0,r0)
122; CHECK: r[[RD2:[0-9]+]]:[[RD3:[0-9]+]] = lsr(r[[RD0]]:[[RD1]],r1)
123define i32 @f13(i32 %a0, i32 %a1) #1 {
124b0:
125  %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a0, i32 %a1)
126  ret i32 %v0
127}
128
129; CHECK-LABEL: f14:
130; CHECK: r[[RE0:[0-9]+]]:[[RE1:[0-9]+]] = rol(r1:0,#47)
131define i64 @f14(i64 %a0, i64 %a1) #1 {
132b0:
133  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a0, i64 17)
134  ret i64 %v0
135}
136
137; CHECK-LABEL: f15:
138; CHECK: r[[RF0:[0-9]+]]:[[RF1:[0-9]+]] = lsr(r1:0,r2)
139; CHECK: r[[RF2:[0-9]+]] = sub(#64,r2)
140; CHECK: r[[RF0]]:[[RF1]] |= asl(r1:0,r[[RF2]])
141define i64 @f15(i64 %a0, i64 %a1) #1 {
142b0:
143  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a0, i64 %a1)
144  ret i64 %v0
145}
146
147; CHECK-LABEL: f16:
148; CHECK: r[[RG0:[0-9]+]]:[[RG1:[0-9]+]] = valignb(r1:0,r3:2,#7)
149define i64 @f16(i64 %a0, i64 %a1) #1 {
150b0:
151  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 8)
152  ret i64 %v0
153}
154
155; CHECK-LABEL: f17:
156; CHECK: r[[RH0:[0-9]+]]:[[RH1:[0-9]+]] = valignb(r1:0,r3:2,#6)
157define i64 @f17(i64 %a0, i64 %a1) #1 {
158b0:
159  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 16)
160  ret i64 %v0
161}
162
163; CHECK-LABEL: f18:
164; CHECK: r[[RI0:[0-9]+]]:[[RI1:[0-9]+]] = valignb(r1:0,r3:2,#5)
165define i64 @f18(i64 %a0, i64 %a1) #1 {
166b0:
167  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 24)
168  ret i64 %v0
169}
170
171; CHECK-LABEL: f19:
172; CHECK: r[[RJ0:[0-9]+]]:[[RJ1:[0-9]+]] = valignb(r1:0,r3:2,#4)
173define i64 @f19(i64 %a0, i64 %a1) #1 {
174b0:
175  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 32)
176  ret i64 %v0
177}
178
179; CHECK-LABEL: f20:
180; CHECK: r[[RK0:[0-9]+]]:[[RK1:[0-9]+]] = valignb(r1:0,r3:2,#3)
181define i64 @f20(i64 %a0, i64 %a1) #1 {
182b0:
183  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 40)
184  ret i64 %v0
185}
186
187; CHECK-LABEL: f21:
188; CHECK: r[[RL0:[0-9]+]]:[[RL1:[0-9]+]] = valignb(r1:0,r3:2,#2)
189define i64 @f21(i64 %a0, i64 %a1) #1 {
190b0:
191  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 48)
192  ret i64 %v0
193}
194
195; CHECK-LABEL: f22:
196; CHECK: r[[RM0:[0-9]+]]:[[RM1:[0-9]+]] = valignb(r1:0,r3:2,#1)
197define i64 @f22(i64 %a0, i64 %a1) #1 {
198b0:
199  %v0 = tail call i64 @llvm.fshl.i64(i64 %a0, i64 %a1, i64 56)
200  ret i64 %v0
201}
202
203; CHECK-LABEL: f23:
204; CHECK: r[[RN0:[0-9]+]]:[[RN1:[0-9]+]] = valignb(r1:0,r3:2,#1)
205define i64 @f23(i64 %a0, i64 %a1) #1 {
206b0:
207  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 8)
208  ret i64 %v0
209}
210
211; CHECK-LABEL: f24:
212; CHECK: r[[RO0:[0-9]+]]:[[RO1:[0-9]+]] = valignb(r1:0,r3:2,#2)
213define i64 @f24(i64 %a0, i64 %a1) #1 {
214b0:
215  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 16)
216  ret i64 %v0
217}
218
219; CHECK-LABEL: f25:
220; CHECK: r[[RP0:[0-9]+]]:[[RP1:[0-9]+]] = valignb(r1:0,r3:2,#3)
221define i64 @f25(i64 %a0, i64 %a1) #1 {
222b0:
223  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 24)
224  ret i64 %v0
225}
226
227; CHECK-LABEL: f26:
228; CHECK: r[[RQ0:[0-9]+]]:[[RQ1:[0-9]+]] = valignb(r1:0,r3:2,#4)
229define i64 @f26(i64 %a0, i64 %a1) #1 {
230b0:
231  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 32)
232  ret i64 %v0
233}
234
235; CHECK-LABEL: f27:
236; CHECK: r[[RR0:[0-9]+]]:[[RR1:[0-9]+]] = valignb(r1:0,r3:2,#5)
237define i64 @f27(i64 %a0, i64 %a1) #1 {
238b0:
239  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 40)
240  ret i64 %v0
241}
242
243; CHECK-LABEL: f28:
244; CHECK: r[[RS0:[0-9]+]]:[[RS1:[0-9]+]] = valignb(r1:0,r3:2,#6)
245define i64 @f28(i64 %a0, i64 %a1) #1 {
246b0:
247  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 48)
248  ret i64 %v0
249}
250
251; CHECK-LABEL: f29:
252; CHECK: r[[RT0:[0-9]+]]:[[RT1:[0-9]+]] = valignb(r1:0,r3:2,#7)
253define i64 @f29(i64 %a0, i64 %a1) #1 {
254b0:
255  %v0 = tail call i64 @llvm.fshr.i64(i64 %a0, i64 %a1, i64 56)
256  ret i64 %v0
257}
258
259; CHECK-LABEL: f30:
260; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
261define i32 @f30(i32 %a0, i32 %a1) #1 {
262b0:
263  %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 16)
264  ret i32 %v0
265}
266
267; CHECK-LABEL: f31:
268; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
269define i32 @f31(i32 %a0, i32 %a1) #1 {
270b0:
271  %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 16)
272  ret i32 %v0
273}
274
275declare i32 @llvm.fshl.i32(i32, i32, i32) #0
276declare i32 @llvm.fshr.i32(i32, i32, i32) #0
277declare i64 @llvm.fshl.i64(i64, i64, i64) #0
278declare i64 @llvm.fshr.i64(i64, i64, i64) #0
279
280attributes #0 = { nounwind readnone speculatable }
281attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-packets" }
282