xref: /llvm-project/llvm/test/CodeGen/Hexagon/fsel.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s
2
3; CHECK-LABEL: danny:
4; CHECK: mux(p0,r1,##1065353216)
5
6define float @danny(i32 %x, float %f) #0 {
7  %t = icmp sgt i32 %x, 0
8  %u = select i1 %t, float %f, float 1.0
9  ret float %u
10}
11
12; CHECK-LABEL: sammy:
13; CHECK: mux(p0,##1069547520,r1)
14
15define float @sammy(i32 %x, float %f) #0 {
16  %t = icmp sgt i32 %x, 0
17  %u = select i1 %t, float 1.5, float %f
18  ret float %u
19}
20
21attributes #0 = { nounwind "target-cpu"="hexagonv5" }
22
23