1; RUN: llc -mtriple=hexagon < %s 2>&1 | FileCheck %s 2 3; Generating a compound instruction with a constant is not profitable. 4; The constant needs to be kept in a register before it is fed to compound 5; instruction. 6; Before, we are generating 7; ra = #65820; 8; rb = lsr(rb, #8); 9; rc ^= and (rb, ra) 10; Now, we are generating 11; ra = and (#65820, lsr(ra, #8)); 12; rb = xor(rb, ra) 13 14; CHECK: and(##65280,lsr(r 15; CHECK-NOT: ^= and 16 17define dso_local zeroext i16 @test_compound(i16 zeroext %varA, i16 zeroext %varB) local_unnamed_addr #0 { 18entry: 19 %tmp = zext i16 %varB to i32 20 %tmp1 = and i16 %varA, 255 21 %tmp2 = zext i16 %tmp1 to i32 22 %.masked.i = and i32 %tmp, 255 23 %tmp3 = xor i32 %.masked.i, %tmp2 24 %tmp4 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp3, i32 255) #2 25 %tmp5 = trunc i64 %tmp4 to i32 26 %tmp6 = and i32 %tmp5, 255 27 %tmp7 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp6, i32 81922) #2 28 %tmp8 = trunc i64 %tmp7 to i32 29 %tmp9 = xor i32 %tmp8, %tmp 30 %tmp10 = lshr i32 %tmp9, 8 31 %tmp11 = lshr i16 %varA, 8 32 %conv2 = zext i16 %tmp11 to i32 33 %tmp12 = and i32 %tmp10, 65280 34 %.masked.i7 = and i32 %tmp10, 255 35 %tmp13 = xor i32 %.masked.i7, %conv2 36 %tmp14 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp13, i32 255) #2 37 %tmp15 = trunc i64 %tmp14 to i32 38 %tmp16 = and i32 %tmp15, 255 39 %tmp17 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp16, i32 81922) #2 40 %tmp18 = trunc i64 %tmp17 to i32 41 %tmp19 = xor i32 %tmp12, %tmp18 42 %tmp20 = lshr i32 %tmp19, 8 43 %tmp21 = trunc i32 %tmp20 to i16 44 ret i16 %tmp21 45} 46 47; Function Attrs: nounwind readnone 48declare i64 @llvm.hexagon.M4.pmpyw(i32, i32) #1 49 50attributes #0 = { nounwind readnone "target-cpu"="hexagonv65" } 51attributes #1 = { nounwind readnone } 52attributes #2 = { nounwind } 53