1; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s 2; Testing for these 5 variants of circular store: 3; Q6_circ_store_update_B(inputLR, pDelay, -1, nConvLength, 4); 4; Q6_circ_store_update_D(inputLR, pDelay, -1, nConvLength, 4); 5; Q6_circ_store_update_HL(inputLR, pDelay, -1, nConvLength, 4); 6; Q6_circ_store_update_HH(inputLR, pDelay, -1, nConvLength, 4); 7; Q6_circ_store_update_W(inputLR, pDelay, -1, nConvLength, 4); 8; producing these 9; memb(r1++#-1:circ(m0)) = r3 10; memd(r1++#-8:circ(m0)) = r1:0 11; memh(r1++#-2:circ(m0)) = r3 12; memh(r1++#-2:circ(m0)) = r3.h 13; memw(r1++#-4:circ(m0)) = r0 14 15target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" 16target triple = "hexagon" 17 18define zeroext i8 @foo1(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 19entry: 20 %conv = zext i16 %filtMemLen to i32 21 %shr2 = lshr i32 %conv, 1 22 %idxprom = sext i16 %filtMemIndex to i32 23 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 24 %or = or i32 %shr2, 33554432 25; CHECK: memb(r{{[0-9]+}}++#-1:circ(m{{[0-1]}})) 26 %0 = tail call ptr @llvm.hexagon.circ.stb(ptr %arrayidx, i32 0, i32 %or, i32 -1) 27 ret i8 0 28} 29 30declare ptr @llvm.hexagon.circ.stb(ptr, i32, i32, i32) nounwind 31 32define i64 @foo2(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 33entry: 34 %conv = zext i16 %filtMemLen to i32 35 %shr1 = lshr i32 %conv, 1 36 %idxprom = sext i16 %filtMemIndex to i32 37 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 38 %shl = shl nuw nsw i32 %shr1, 3 39 %or = or i32 %shl, 83886080 40; CHECK: memd(r{{[0-9]+}}++#-8:circ(m{{[0-1]}})) 41 %0 = tail call ptr @llvm.hexagon.circ.std(ptr %arrayidx, i64 undef, i32 %or, i32 -8) 42 ret i64 0 43} 44 45declare ptr @llvm.hexagon.circ.std(ptr, i64, i32, i32) nounwind 46 47define signext i16 @foo3(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 48entry: 49 %conv = zext i16 %filtMemLen to i32 50 %shr2 = and i32 %conv, 65534 51 %idxprom = sext i16 %filtMemIndex to i32 52 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 53 %or = or i32 %shr2, 50331648 54; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}})) 55 %0 = tail call ptr @llvm.hexagon.circ.sth(ptr %arrayidx, i32 0, i32 %or, i32 -2) 56 ret i16 0 57} 58 59declare ptr @llvm.hexagon.circ.sth(ptr, i32, i32, i32) nounwind 60 61define signext i16 @foo5(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 62entry: 63 %conv = zext i16 %filtMemLen to i32 64 %shr2 = and i32 %conv, 65534 65 %idxprom = sext i16 %filtMemIndex to i32 66 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 67 %or = or i32 %shr2, 50331648 68; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}})) = r{{[0-9]*}}.h 69 %0 = tail call ptr @llvm.hexagon.circ.sthhi(ptr %arrayidx, i32 0, i32 %or, i32 -2) 70 ret i16 0 71} 72 73declare ptr @llvm.hexagon.circ.sthhi(ptr, i32, i32, i32) nounwind 74 75define i32 @foo6(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 76entry: 77 %conv = zext i16 %filtMemLen to i32 78 %shr1 = lshr i32 %conv, 1 79 %idxprom = sext i16 %filtMemIndex to i32 80 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 81 %shl = shl nuw nsw i32 %shr1, 2 82 %or = or i32 %shl, 67108864 83; CHECK: memw(r{{[0-9]+}}++#-4:circ(m{{[0-1]}})) 84 %0 = tail call ptr @llvm.hexagon.circ.stw(ptr %arrayidx, i32 undef, i32 %or, i32 -4) 85 ret i32 0 86} 87 88declare ptr @llvm.hexagon.circ.stw(ptr, i32, i32, i32) nounwind 89 90!0 = !{!"omnipotent char", !1} 91!1 = !{!"Simple C/C++ TBAA"} 92!2 = !{!"short", !0} 93!3 = !{!"int", !0} 94