1; RUN: llc -mtriple=hexagon < %s | FileCheck %s 2; Testing for these 6 variants of circular load: 3; Q6_circ_load_update_B(inputLR, pDelay, -1, nConvLength, 4); 4; Q6_circ_load_update_D(inputLR, pDelay, -1, nConvLength, 4); 5; Q6_circ_load_update_H(inputLR, pDelay, -1, nConvLength, 4); 6; Q6_circ_load_update_UB(inputLR, pDelay, -1, nConvLength, 4); 7; Q6_circ_load_update_UH(inputLR, pDelay, -1, nConvLength, 4); 8; Q6_circ_load_update_W(inputLR, pDelay, -1, nConvLength, 4); 9; producing these: 10; r0 = memb(r1++#-1:circ(m0)) 11; r3:2 = memd(r1++#-8:circ(m0)) 12; r0 = memh(r1++#-2:circ(m0)) 13; r0 = memub(r1++#-1:circ(m0)) 14; r0 = memuh(r1++#-2:circ(m0)) 15; r0 = memw(r1++#-4:circ(m0)) 16 17target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" 18target triple = "hexagon" 19 20define signext i8 @foo1(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 21entry: 22 %inputLR = alloca i8, align 1 23 %conv = zext i16 %filtMemLen to i32 24 %shr1 = lshr i32 %conv, 1 25 %idxprom = sext i16 %filtMemIndex to i32 26 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 27 %or = or i32 %shr1, 33554432 28; CHECK: = memb(r{{[0-9]+}}++#-1:circ(m{{[0-1]}})) 29 %0 = call ptr @llvm.hexagon.circ.ldb(ptr %arrayidx, ptr %inputLR, i32 %or, i32 -1) 30 %1 = load i8, ptr %inputLR, align 1, !tbaa !0 31 ret i8 %1 32} 33 34declare ptr @llvm.hexagon.circ.ldb(ptr, ptr, i32, i32) nounwind 35 36define i64 @foo2(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 37entry: 38 %inputLR = alloca i64, align 8 39 %conv = zext i16 %filtMemLen to i32 40 %shr1 = lshr i32 %conv, 1 41 %idxprom = sext i16 %filtMemIndex to i32 42 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 43 %shl = shl nuw nsw i32 %shr1, 3 44 %or = or i32 %shl, 83886080 45; CHECK: = memd(r{{[0-9]+}}++#-8:circ(m{{[0-1]}})) 46 %0 = call ptr @llvm.hexagon.circ.ldd(ptr %arrayidx, ptr %inputLR, i32 %or, i32 -8) 47 %1 = load i64, ptr %inputLR, align 8, !tbaa !0 48 ret i64 %1 49} 50 51declare ptr @llvm.hexagon.circ.ldd(ptr, ptr, i32, i32) nounwind 52 53define signext i16 @foo3(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 54entry: 55 %inputLR = alloca i16, align 2 56 %conv = zext i16 %filtMemLen to i32 57 %shr1 = and i32 %conv, 65534 58 %idxprom = sext i16 %filtMemIndex to i32 59 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 60 %or = or i32 %shr1, 50331648 61; CHECK: = memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}})) 62 %0 = call ptr @llvm.hexagon.circ.ldh(ptr %arrayidx, ptr %inputLR, i32 %or, i32 -2) 63 %1 = load i16, ptr %inputLR, align 2, !tbaa !2 64 ret i16 %1 65} 66 67declare ptr @llvm.hexagon.circ.ldh(ptr, ptr, i32, i32) nounwind 68 69define zeroext i8 @foo4(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 70entry: 71 %inputLR = alloca i8, align 1 72 %conv = zext i16 %filtMemLen to i32 73 %shr1 = lshr i32 %conv, 1 74 %idxprom = sext i16 %filtMemIndex to i32 75 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 76 %or = or i32 %shr1, 33554432 77; CHECK: = memub(r{{[0-9]+}}++#-1:circ(m{{[0-1]}})) 78 %0 = call ptr @llvm.hexagon.circ.ldub(ptr %arrayidx, ptr %inputLR, i32 %or, i32 -1) 79 %1 = load i8, ptr %inputLR, align 1, !tbaa !0 80 ret i8 %1 81} 82 83declare ptr @llvm.hexagon.circ.ldub(ptr, ptr, i32, i32) nounwind 84 85define zeroext i16 @foo5(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 86entry: 87 %inputLR = alloca i16, align 2 88 %conv = zext i16 %filtMemLen to i32 89 %shr1 = and i32 %conv, 65534 90 %idxprom = sext i16 %filtMemIndex to i32 91 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 92 %or = or i32 %shr1, 50331648 93; CHECK: = memuh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}})) 94 %0 = call ptr @llvm.hexagon.circ.lduh(ptr %arrayidx, ptr %inputLR, i32 %or, i32 -2) 95 %1 = load i16, ptr %inputLR, align 2, !tbaa !2 96 ret i16 %1 97} 98 99declare ptr @llvm.hexagon.circ.lduh(ptr, ptr, i32, i32) nounwind 100 101define i32 @foo6(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind { 102entry: 103 %inputLR = alloca i32, align 4 104 %conv = zext i16 %filtMemLen to i32 105 %shr1 = lshr i32 %conv, 1 106 %idxprom = sext i16 %filtMemIndex to i32 107 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom 108 %shl = shl nuw nsw i32 %shr1, 2 109 %or = or i32 %shl, 67108864 110; CHECK: = memw(r{{[0-9]+}}++#-4:circ(m{{[0-1]}})) 111 %0 = call ptr @llvm.hexagon.circ.ldw(ptr %arrayidx, ptr %inputLR, i32 %or, i32 -4) 112 %1 = load i32, ptr %inputLR, align 4, !tbaa !3 113 ret i32 %1 114} 115 116declare ptr @llvm.hexagon.circ.ldw(ptr, ptr, i32, i32) nounwind 117 118!0 = !{!"omnipotent char", !1} 119!1 = !{!"Simple C/C++ TBAA"} 120!2 = !{!"short", !0} 121!3 = !{!"int", !0} 122