1; RUN: llc -mtriple=hexagon -O3 < %s 2; REQUIRES: asserts 3 4target triple = "hexagon-unknown--elf" 5 6; Function Attrs: nounwind 7define void @f0(i32 %a0, i32 %a1) #0 { 8b0: 9 %v0 = alloca [8 x i32], align 8 10 call void @llvm.memset.p0.i32(ptr align 8 %v0, i8 0, i32 32, i1 false) 11 %v2 = icmp sgt i32 %a0, 0 12 br i1 %v2, label %b1, label %b18 13 14b1: ; preds = %b0 15 %v3 = getelementptr inbounds [8 x i32], ptr %v0, i32 0, i32 6 16 %v4 = inttoptr i32 %a1 to ptr 17 %v5 = add i32 %a0, -1 18 %v6 = icmp sgt i32 %v5, 0 19 br i1 %v6, label %b2, label %b13 20 21b2: ; preds = %b1 22 %v8 = getelementptr [8 x i32], ptr %v0, i32 0, i32 1 23 %v9 = getelementptr [8 x i32], ptr %v0, i32 0, i32 2 24 %v10 = getelementptr [8 x i32], ptr %v0, i32 0, i32 3 25 %v11 = getelementptr [8 x i32], ptr %v0, i32 0, i32 4 26 %v12 = getelementptr [8 x i32], ptr %v0, i32 0, i32 5 27 %v13 = getelementptr [8 x i32], ptr %v0, i32 0, i32 6 28 %v14 = getelementptr [8 x i32], ptr %v0, i32 0, i32 7 29 %v15 = add i32 %a0, -2 30 %v16 = lshr i32 %v15, 1 31 %v17 = add i32 %v16, 1 32 %v18 = urem i32 %v17, 2 33 %v19 = icmp ne i32 %v18, 0 34 %v20 = add i32 %v5, -2 35 %v21 = icmp ugt i32 %v17, 1 36 br i1 %v21, label %b3, label %b7 37 38b3: ; preds = %b2 39 br label %b4 40 41b4: ; preds = %b22, %b3 42 %v22 = phi i32 [ 0, %b3 ], [ %v124, %b22 ] 43 %v23 = phi i32 [ 0, %b3 ], [ %v136, %b22 ] 44 %v24 = mul nsw i32 %v22, 4 45 %v25 = add nsw i32 %v24, 268435456 46 %v26 = inttoptr i32 %v25 to ptr 47 store volatile i32 %a1, ptr %v26, align 4, !tbaa !0 48 %v27 = load i32, ptr %v0, align 8, !tbaa !0 49 store volatile i32 %v27, ptr %v4, align 4, !tbaa !0 50 %v28 = load i32, ptr %v8, align 4, !tbaa !0 51 store volatile i32 %v28, ptr %v4, align 4, !tbaa !0 52 %v29 = load i32, ptr %v9, align 8, !tbaa !0 53 store volatile i32 %v29, ptr %v4, align 4, !tbaa !0 54 %v30 = load i32, ptr %v10, align 4, !tbaa !0 55 store volatile i32 %v30, ptr %v4, align 4, !tbaa !0 56 %v31 = load i32, ptr %v11, align 8, !tbaa !0 57 store volatile i32 %v31, ptr %v4, align 4, !tbaa !0 58 %v32 = load i32, ptr %v12, align 4, !tbaa !0 59 store volatile i32 %v32, ptr %v4, align 4, !tbaa !0 60 %v33 = load i32, ptr %v13, align 8, !tbaa !0 61 store volatile i32 %v33, ptr %v4, align 4, !tbaa !0 62 %v34 = load i32, ptr %v14, align 4, !tbaa !0 63 store volatile i32 %v34, ptr %v4, align 4, !tbaa !0 64 %v35 = icmp eq i32 %v23, 0 65 br i1 %v35, label %b19, label %b20 66 67b5: ; preds = %b22 68 %v36 = phi i32 [ %v136, %b22 ] 69 %v37 = phi i32 [ %v124, %b22 ] 70 br i1 %v19, label %b6, label %b12 71 72b6: ; preds = %b5 73 br label %b7 74 75b7: ; preds = %b6, %b2 76 %v38 = phi i32 [ 0, %b2 ], [ %v36, %b6 ] 77 %v39 = phi i32 [ 0, %b2 ], [ %v37, %b6 ] 78 br label %b8 79 80b8: ; preds = %b10, %b7 81 %v40 = phi i32 [ %v39, %b7 ], [ %v54, %b10 ] 82 %v41 = phi i32 [ %v38, %b7 ], [ %v66, %b10 ] 83 %v42 = mul nsw i32 %v40, 4 84 %v43 = add nsw i32 %v42, 268435456 85 %v44 = inttoptr i32 %v43 to ptr 86 store volatile i32 %a1, ptr %v44, align 4, !tbaa !0 87 %v45 = load i32, ptr %v0, align 8, !tbaa !0 88 store volatile i32 %v45, ptr %v4, align 4, !tbaa !0 89 %v46 = load i32, ptr %v8, align 4, !tbaa !0 90 store volatile i32 %v46, ptr %v4, align 4, !tbaa !0 91 %v47 = load i32, ptr %v9, align 8, !tbaa !0 92 store volatile i32 %v47, ptr %v4, align 4, !tbaa !0 93 %v48 = load i32, ptr %v10, align 4, !tbaa !0 94 store volatile i32 %v48, ptr %v4, align 4, !tbaa !0 95 %v49 = load i32, ptr %v11, align 8, !tbaa !0 96 store volatile i32 %v49, ptr %v4, align 4, !tbaa !0 97 %v50 = load i32, ptr %v12, align 4, !tbaa !0 98 store volatile i32 %v50, ptr %v4, align 4, !tbaa !0 99 %v51 = load i32, ptr %v13, align 8, !tbaa !0 100 store volatile i32 %v51, ptr %v4, align 4, !tbaa !0 101 %v52 = load i32, ptr %v14, align 4, !tbaa !0 102 store volatile i32 %v52, ptr %v4, align 4, !tbaa !0 103 %v53 = icmp eq i32 %v41, 0 104 br i1 %v53, label %b9, label %b10 105 106b9: ; preds = %b8 107 store i32 0, ptr %v3, align 8, !tbaa !0 108 br label %b10 109 110b10: ; preds = %b9, %b8 111 %v54 = phi i32 [ 3, %b9 ], [ %v40, %b8 ] 112 %v55 = mul nsw i32 %v54, 4 113 %v56 = add nsw i32 %v55, 268435456 114 %v57 = inttoptr i32 %v56 to ptr 115 store volatile i32 %a1, ptr %v57, align 4, !tbaa !0 116 %v58 = load i32, ptr %v0, align 8, !tbaa !0 117 store volatile i32 %v58, ptr %v4, align 4, !tbaa !0 118 %v59 = load i32, ptr %v8, align 4, !tbaa !0 119 store volatile i32 %v59, ptr %v4, align 4, !tbaa !0 120 %v60 = load i32, ptr %v9, align 8, !tbaa !0 121 store volatile i32 %v60, ptr %v4, align 4, !tbaa !0 122 %v61 = load i32, ptr %v10, align 4, !tbaa !0 123 store volatile i32 %v61, ptr %v4, align 4, !tbaa !0 124 %v62 = load i32, ptr %v11, align 8, !tbaa !0 125 store volatile i32 %v62, ptr %v4, align 4, !tbaa !0 126 %v63 = load i32, ptr %v12, align 4, !tbaa !0 127 store volatile i32 %v63, ptr %v4, align 4, !tbaa !0 128 %v64 = load i32, ptr %v13, align 8, !tbaa !0 129 store volatile i32 %v64, ptr %v4, align 4, !tbaa !0 130 %v65 = load i32, ptr %v14, align 4, !tbaa !0 131 store volatile i32 %v65, ptr %v4, align 4, !tbaa !0 132 %v66 = add nsw i32 %v41, 2 133 %v67 = icmp slt i32 %v66, %v5 134 br i1 %v67, label %b8, label %b11 135 136b11: ; preds = %b10 137 %v68 = phi i32 [ %v66, %b10 ] 138 %v69 = phi i32 [ %v54, %b10 ] 139 br label %b12 140 141b12: ; preds = %b11, %b5 142 %v70 = phi i32 [ %v36, %b5 ], [ %v68, %b11 ] 143 %v71 = phi i32 [ %v37, %b5 ], [ %v69, %b11 ] 144 %v72 = icmp eq i32 %v70, %a0 145 br i1 %v72, label %b18, label %b13 146 147b13: ; preds = %b12, %b1 148 %v73 = phi i32 [ 0, %b1 ], [ %v70, %b12 ] 149 %v74 = phi i32 [ 0, %b1 ], [ %v71, %b12 ] 150 %v76 = getelementptr [8 x i32], ptr %v0, i32 0, i32 1 151 %v77 = getelementptr [8 x i32], ptr %v0, i32 0, i32 2 152 %v78 = getelementptr [8 x i32], ptr %v0, i32 0, i32 3 153 %v79 = getelementptr [8 x i32], ptr %v0, i32 0, i32 4 154 %v80 = getelementptr [8 x i32], ptr %v0, i32 0, i32 5 155 %v81 = getelementptr [8 x i32], ptr %v0, i32 0, i32 6 156 %v82 = getelementptr [8 x i32], ptr %v0, i32 0, i32 7 157 br label %b14 158 159b14: ; preds = %b16, %b13 160 %v83 = phi i32 [ %v74, %b13 ], [ %v86, %b16 ] 161 %v84 = phi i32 [ %v73, %b13 ], [ %v98, %b16 ] 162 %v85 = icmp eq i32 %v84, 1 163 br i1 %v85, label %b15, label %b16 164 165b15: ; preds = %b14 166 store i32 0, ptr %v3, align 8, !tbaa !0 167 br label %b16 168 169b16: ; preds = %b15, %b14 170 %v86 = phi i32 [ 3, %b15 ], [ %v83, %b14 ] 171 %v87 = mul nsw i32 %v86, 4 172 %v88 = add nsw i32 %v87, 268435456 173 %v89 = inttoptr i32 %v88 to ptr 174 store volatile i32 %a1, ptr %v89, align 4, !tbaa !0 175 %v90 = load i32, ptr %v0, align 8, !tbaa !0 176 store volatile i32 %v90, ptr %v4, align 4, !tbaa !0 177 %v91 = load i32, ptr %v76, align 4, !tbaa !0 178 store volatile i32 %v91, ptr %v4, align 4, !tbaa !0 179 %v92 = load i32, ptr %v77, align 8, !tbaa !0 180 store volatile i32 %v92, ptr %v4, align 4, !tbaa !0 181 %v93 = load i32, ptr %v78, align 4, !tbaa !0 182 store volatile i32 %v93, ptr %v4, align 4, !tbaa !0 183 %v94 = load i32, ptr %v79, align 8, !tbaa !0 184 store volatile i32 %v94, ptr %v4, align 4, !tbaa !0 185 %v95 = load i32, ptr %v80, align 4, !tbaa !0 186 store volatile i32 %v95, ptr %v4, align 4, !tbaa !0 187 %v96 = load i32, ptr %v81, align 8, !tbaa !0 188 store volatile i32 %v96, ptr %v4, align 4, !tbaa !0 189 %v97 = load i32, ptr %v82, align 4, !tbaa !0 190 store volatile i32 %v97, ptr %v4, align 4, !tbaa !0 191 %v98 = add nsw i32 %v84, 1 192 %v99 = icmp eq i32 %v98, %a0 193 br i1 %v99, label %b17, label %b14 194 195b17: ; preds = %b16 196 br label %b18 197 198b18: ; preds = %b17, %b12, %b0 199 ret void 200 201b19: ; preds = %b4 202 store i32 0, ptr %v3, align 8, !tbaa !0 203 br label %b20 204 205b20: ; preds = %b19, %b4 206 %v100 = phi i32 [ 3, %b19 ], [ %v22, %b4 ] 207 %v101 = mul nsw i32 %v100, 4 208 %v102 = add nsw i32 %v101, 268435456 209 %v103 = inttoptr i32 %v102 to ptr 210 store volatile i32 %a1, ptr %v103, align 4, !tbaa !0 211 %v104 = load i32, ptr %v0, align 8, !tbaa !0 212 store volatile i32 %v104, ptr %v4, align 4, !tbaa !0 213 %v105 = load i32, ptr %v8, align 4, !tbaa !0 214 store volatile i32 %v105, ptr %v4, align 4, !tbaa !0 215 %v106 = load i32, ptr %v9, align 8, !tbaa !0 216 store volatile i32 %v106, ptr %v4, align 4, !tbaa !0 217 %v107 = load i32, ptr %v10, align 4, !tbaa !0 218 store volatile i32 %v107, ptr %v4, align 4, !tbaa !0 219 %v108 = load i32, ptr %v11, align 8, !tbaa !0 220 store volatile i32 %v108, ptr %v4, align 4, !tbaa !0 221 %v109 = load i32, ptr %v12, align 4, !tbaa !0 222 store volatile i32 %v109, ptr %v4, align 4, !tbaa !0 223 %v110 = load i32, ptr %v13, align 8, !tbaa !0 224 store volatile i32 %v110, ptr %v4, align 4, !tbaa !0 225 %v111 = load i32, ptr %v14, align 4, !tbaa !0 226 store volatile i32 %v111, ptr %v4, align 4, !tbaa !0 227 %v112 = add nsw i32 %v23, 2 228 %v113 = mul nsw i32 %v100, 4 229 %v114 = add nsw i32 %v113, 268435456 230 %v115 = inttoptr i32 %v114 to ptr 231 store volatile i32 %a1, ptr %v115, align 4, !tbaa !0 232 %v116 = load i32, ptr %v0, align 8, !tbaa !0 233 store volatile i32 %v116, ptr %v4, align 4, !tbaa !0 234 %v117 = load i32, ptr %v8, align 4, !tbaa !0 235 store volatile i32 %v117, ptr %v4, align 4, !tbaa !0 236 %v118 = load i32, ptr %v9, align 8, !tbaa !0 237 store volatile i32 %v118, ptr %v4, align 4, !tbaa !0 238 %v119 = load i32, ptr %v10, align 4, !tbaa !0 239 store volatile i32 %v119, ptr %v4, align 4, !tbaa !0 240 %v120 = load i32, ptr %v11, align 8, !tbaa !0 241 store volatile i32 %v120, ptr %v4, align 4, !tbaa !0 242 %v121 = load i32, ptr %v12, align 4, !tbaa !0 243 store volatile i32 %v121, ptr %v4, align 4, !tbaa !0 244 %v122 = load i32, ptr %v13, align 8, !tbaa !0 245 store volatile i32 %v122, ptr %v4, align 4, !tbaa !0 246 %v123 = load i32, ptr %v14, align 4, !tbaa !0 247 store volatile i32 %v123, ptr %v4, align 4, !tbaa !0 248 br i1 false, label %b21, label %b22 249 250b21: ; preds = %b20 251 store i32 0, ptr %v3, align 8, !tbaa !0 252 br label %b22 253 254b22: ; preds = %b21, %b20 255 %v124 = phi i32 [ 3, %b21 ], [ %v100, %b20 ] 256 %v125 = mul nsw i32 %v124, 4 257 %v126 = add nsw i32 %v125, 268435456 258 %v127 = inttoptr i32 %v126 to ptr 259 store volatile i32 %a1, ptr %v127, align 4, !tbaa !0 260 %v128 = load i32, ptr %v0, align 8, !tbaa !0 261 store volatile i32 %v128, ptr %v4, align 4, !tbaa !0 262 %v129 = load i32, ptr %v8, align 4, !tbaa !0 263 store volatile i32 %v129, ptr %v4, align 4, !tbaa !0 264 %v130 = load i32, ptr %v9, align 8, !tbaa !0 265 store volatile i32 %v130, ptr %v4, align 4, !tbaa !0 266 %v131 = load i32, ptr %v10, align 4, !tbaa !0 267 store volatile i32 %v131, ptr %v4, align 4, !tbaa !0 268 %v132 = load i32, ptr %v11, align 8, !tbaa !0 269 store volatile i32 %v132, ptr %v4, align 4, !tbaa !0 270 %v133 = load i32, ptr %v12, align 4, !tbaa !0 271 store volatile i32 %v133, ptr %v4, align 4, !tbaa !0 272 %v134 = load i32, ptr %v13, align 8, !tbaa !0 273 store volatile i32 %v134, ptr %v4, align 4, !tbaa !0 274 %v135 = load i32, ptr %v14, align 4, !tbaa !0 275 store volatile i32 %v135, ptr %v4, align 4, !tbaa !0 276 %v136 = add nsw i32 %v112, 2 277 %v137 = icmp slt i32 %v136, %v20 278 br i1 %v137, label %b4, label %b5 279} 280 281; Function Attrs: nounwind 282define void @f1(i32 %a0, i32 %a1) #0 { 283b0: 284 tail call void @f0(i32 %a0, i32 %a1) 285 ret void 286} 287 288; Function Attrs: argmemonly nounwind 289declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) #1 290 291attributes #0 = { nounwind } 292attributes #1 = { argmemonly nounwind } 293 294!0 = !{!1, !1, i64 0} 295!1 = !{!"long", !2, i64 0} 296!2 = !{!"omnipotent char", !3, i64 0} 297!3 = !{!"Simple C/C++ TBAA"} 298