xref: /llvm-project/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; Check that we don't crash.
3; CHECK: vshuff
4
5target triple = "hexagon"
6
7define void @f0(ptr %a0) #0 {
8entry:
9  %v0 = icmp eq i32 undef, 0
10  %v1 = select i1 %v0, <32 x i16> undef, <32 x i16> zeroinitializer
11  %v2 = bitcast <32 x i16> %v1 to <16 x i32>
12  %v3 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %v2)
13  store <16 x i32> %v3, ptr %a0, align 2
14  ret void
15}
16
17; Function Attrs: nounwind readnone
18declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
19
20attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
21attributes #1 = { nounwind readnone }
22