xref: /llvm-project/llvm/test/CodeGen/Hexagon/base-offset-stv4.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s
2; REQUIRES: asserts
3
4; Function Attrs: nounwind
5define void @f0() #0 {
6b0:
7  br i1 undef, label %b1, label %b4
8
9b1:                                               ; preds = %b0
10  %v0 = load ptr, ptr undef, align 4
11  br label %b2
12
13b2:                                               ; preds = %b2, %b1
14  %v1 = phi i32 [ 13, %b1 ], [ %v5, %b2 ]
15  %v2 = getelementptr inbounds i16, ptr %v0, i32 %v1
16  %v3 = add nsw i32 0, %v1
17  %v4 = getelementptr inbounds i16, ptr %v0, i32 %v3
18  store i16 0, ptr %v4, align 2
19  store i16 0, ptr %v2, align 2
20  %v5 = add i32 %v1, 1
21  %v6 = icmp eq i32 %v5, 26
22  br i1 %v6, label %b3, label %b2
23
24b3:                                               ; preds = %b3, %b2
25  br i1 undef, label %b4, label %b3
26
27b4:                                               ; preds = %b3, %b0
28  ret void
29}
30
31attributes #0 = { nounwind }
32