xref: /llvm-project/llvm/test/CodeGen/Hexagon/autohvx/abs.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=hexagon < %s | FileCheck %s
3
4define <128 x i8> @abs80(<128 x i8> %a0) #0 {
5; CHECK-LABEL: abs80:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    {
8; CHECK-NEXT:     v3:2.h = vsxt(v0.b)
9; CHECK-NEXT:    }
10; CHECK-NEXT:    {
11; CHECK-NEXT:     v3:2.b = vshuffoe(v3.b,v2.b)
12; CHECK-NEXT:    }
13; CHECK-NEXT:    {
14; CHECK-NEXT:     v1.b = vadd(v0.b,v3.b)
15; CHECK-NEXT:    }
16; CHECK-NEXT:    {
17; CHECK-NEXT:     v0 = vxor(v0,v1)
18; CHECK-NEXT:     jumpr r31
19; CHECK-NEXT:    }
20  %v0 = sub <128 x i8> zeroinitializer, %a0
21  %v1 = icmp sgt <128 x i8> %a0, zeroinitializer
22  %v2 = select <128 x i1> %v1, <128 x i8> %a0, <128 x i8> %v0
23  ret <128 x i8> %v2
24}
25
26define <128 x i8> @abs81(<128 x i8> %a0) #1 {
27; CHECK-LABEL: abs81:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    {
30; CHECK-NEXT:     v0.b = vabs(v0.b)
31; CHECK-NEXT:     jumpr r31
32; CHECK-NEXT:    }
33  %v0 = sub <128 x i8> zeroinitializer, %a0
34  %v1 = icmp sgt <128 x i8> %a0, zeroinitializer
35  %v2 = select <128 x i1> %v1, <128 x i8> %a0, <128 x i8> %v0
36  ret <128 x i8> %v2
37}
38
39define <64 x i16> @abs16(<64 x i16> %a0) #0 {
40; CHECK-LABEL: abs16:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    {
43; CHECK-NEXT:     v0.h = vabs(v0.h)
44; CHECK-NEXT:     jumpr r31
45; CHECK-NEXT:    }
46  %v0 = sub <64 x i16> zeroinitializer, %a0
47  %v1 = icmp sgt <64 x i16> %a0, zeroinitializer
48  %v2 = select <64 x i1> %v1, <64 x i16> %a0, <64 x i16> %v0
49  ret <64 x i16> %v2
50}
51
52define <32 x i32> @abs32(<32 x i32> %a0) #0 {
53; CHECK-LABEL: abs32:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    {
56; CHECK-NEXT:     v0.w = vabs(v0.w)
57; CHECK-NEXT:     jumpr r31
58; CHECK-NEXT:    }
59  %v0 = sub <32 x i32> zeroinitializer, %a0
60  %v1 = icmp sgt <32 x i32> %a0, zeroinitializer
61  %v2 = select <32 x i1> %v1, <32 x i32> %a0, <32 x i32> %v0
62  ret <32 x i32> %v2
63}
64
65attributes #0 = { nounwind readnone "target-features"="+hvxv60,+hvx-length128b" }
66attributes #1 = { nounwind readnone "target-features"="+hvxv62,+hvx-length128b" }
67