xref: /llvm-project/llvm/test/CodeGen/Hexagon/absimm.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; Check that we generate absolute addressing mode instructions
3; with immediate value.
4
5define i32 @f1(i32 %i) nounwind {
6; CHECK: memw(##786432) = r{{[0-9]+}}
7entry:
8  store volatile i32 %i, ptr inttoptr (i32 786432 to ptr), align 262144
9  ret i32 %i
10}
11
12define ptr @f2(ptr nocapture %i) nounwind {
13entry:
14; CHECK: r{{[0-9]+}} = memw(##786432)
15  %0 = load volatile i32, ptr inttoptr (i32 786432 to ptr), align 262144
16  %1 = inttoptr i32 %0 to ptr
17  ret ptr %1
18  }
19