xref: /llvm-project/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2
3; This test checks that S2_tstbit_i instruction is generated
4; and it does not assert.
5
6; CHECK: p{{[0-9]+}} = tstbit
7
8
9target triple = "hexagon-unknown-unknown-elf"
10
11%struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192 = type { ptr, ptr }
12
13@.str.8 = external dso_local unnamed_addr constant [5 x i8], align 1
14
15declare dso_local void @panic(ptr, ...) local_unnamed_addr
16
17define dso_local fastcc void @elv_rqhash_find() unnamed_addr {
18entry:
19  %cmd_flags = getelementptr inbounds %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192, ptr null, i32 -5
20  %0 = load i64, ptr %cmd_flags, align 8
21  %1 = and i64 %0, 4294967296
22  %tobool10 = icmp eq i64 %1, 0
23  br i1 %tobool10, label %do.body11, label %do.end14
24
25do.body11:                                        ; preds = %entry
26  tail call void (ptr, ...) @panic(ptr @.str.8) #1
27  unreachable
28
29do.end14:                                         ; preds = %entry
30  %and.i = and i64 %0, -4294967297
31  store i64 %and.i, ptr %cmd_flags, align 8
32  ret void
33}
34