xref: /llvm-project/llvm/test/CodeGen/DirectX/HLSLControlFlowHint.ll (revision 380bb51b70b6d9f3da07a87f56fc3fe44bc78691) 
1; RUN: opt -S -dxil-op-lower -dxil-translate-metadata -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s
2
3; This test make sure LLVM metadata is being translated into DXIL.
4
5
6; CHECK: define i32 @test_branch(i32 %X)
7; CHECK-NOT: hlsl.controlflow.hint
8; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_BRANCH:![0-9]+]]
9define i32 @test_branch(i32 %X) {
10entry:
11  %X.addr = alloca i32, align 4
12  %resp = alloca i32, align 4
13  store i32 %X, ptr %X.addr, align 4
14  %0 = load i32, ptr %X.addr, align 4
15  %cmp = icmp sgt i32 %0, 0
16  br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !0
17
18if.then:                                          ; preds = %entry
19  %1 = load i32, ptr %X.addr, align 4
20  %sub = sub nsw i32 0, %1
21  store i32 %sub, ptr %resp, align 4
22  br label %if.end
23
24if.else:                                          ; preds = %entry
25  %2 = load i32, ptr %X.addr, align 4
26  %mul = mul nsw i32 %2, 2
27  store i32 %mul, ptr %resp, align 4
28  br label %if.end
29
30if.end:                                           ; preds = %if.else, %if.then
31  %3 = load i32, ptr %resp, align 4
32  ret i32 %3
33}
34
35
36; CHECK: define i32 @test_flatten(i32 %X)
37; CHECK-NOT: hlsl.controlflow.hint
38; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_FLATTEN:![0-9]+]]
39define i32 @test_flatten(i32 %X) {
40entry:
41  %X.addr = alloca i32, align 4
42  %resp = alloca i32, align 4
43  store i32 %X, ptr %X.addr, align 4
44  %0 = load i32, ptr %X.addr, align 4
45  %cmp = icmp sgt i32 %0, 0
46  br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !1
47
48if.then:                                          ; preds = %entry
49  %1 = load i32, ptr %X.addr, align 4
50  %sub = sub nsw i32 0, %1
51  store i32 %sub, ptr %resp, align 4
52  br label %if.end
53
54if.else:                                          ; preds = %entry
55  %2 = load i32, ptr %X.addr, align 4
56  %mul = mul nsw i32 %2, 2
57  store i32 %mul, ptr %resp, align 4
58  br label %if.end
59
60if.end:                                           ; preds = %if.else, %if.then
61  %3 = load i32, ptr %resp, align 4
62  ret i32 %3
63}
64
65
66; CHECK: define i32 @test_no_attr(i32 %X)
67; CHECK-NOT: hlsl.controlflow.hint
68; CHECK-NOT: !dx.controlflow.hints
69define i32 @test_no_attr(i32 %X) {
70entry:
71  %X.addr = alloca i32, align 4
72  %resp = alloca i32, align 4
73  store i32 %X, ptr %X.addr, align 4
74  %0 = load i32, ptr %X.addr, align 4
75  %cmp = icmp sgt i32 %0, 0
76  br i1 %cmp, label %if.then, label %if.else
77
78if.then:                                          ; preds = %entry
79  %1 = load i32, ptr %X.addr, align 4
80  %sub = sub nsw i32 0, %1
81  store i32 %sub, ptr %resp, align 4
82  br label %if.end
83
84if.else:                                          ; preds = %entry
85  %2 = load i32, ptr %X.addr, align 4
86  %mul = mul nsw i32 %2, 2
87  store i32 %mul, ptr %resp, align 4
88  br label %if.end
89
90if.end:                                           ; preds = %if.else, %if.then
91  %3 = load i32, ptr %resp, align 4
92  ret i32 %3
93}
94; CHECK-NOT: hlsl.controlflow.hint
95; CHECK: [[HINT_BRANCH]] = !{!"dx.controlflow.hints", i32 1}
96; CHECK: [[HINT_FLATTEN]] = !{!"dx.controlflow.hints", i32 2}
97!0 = !{!"hlsl.controlflow.hint", i32 1}
98!1 = !{!"hlsl.controlflow.hint", i32 2}
99