xref: /llvm-project/llvm/test/CodeGen/CSKY/rotl.ll (revision a556ec8861df920bfaee3057df8aac739aa59b24)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 < %s -mtriple=csky | FileCheck %s
3
4define i32 @ROTLI32(i32 %x) {
5; CHECK-LABEL: ROTLI32:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    rotli32 a0, a0, 4
8; CHECK-NEXT:    rts16
9entry:
10  %shl = shl i32 %x, 4
11  %shr = lshr i32 %x, 28
12  %or = or i32 %shl, %shr
13  ret i32 %or
14}
15
16define i32 @ROTL32(i32 %x, i32 %y) {
17; CHECK-LABEL: ROTL32:
18; CHECK:       # %bb.0: # %entry
19; CHECK-NEXT:    andi32 a1, a1, 31
20; CHECK-NEXT:    rotl16 a0, a1
21; CHECK-NEXT:    rts16
22entry:
23  %0 = shl i32 %x, %y
24  %1 = sub i32 32, %y
25  %2 = lshr i32 %x, %1
26  %3 = or i32 %2, %0
27  ret i32 %3
28}
29