1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=avr -mtriple=avr -verify-machineinstrs | FileCheck %s 3 4; Optimize for speed. 5define i8 @shift_i8_i8_speed(i8 %a, i8 %b) { 6; CHECK-LABEL: shift_i8_i8_speed: 7; CHECK: ; %bb.0: 8; CHECK-NEXT: dec r22 9; CHECK-NEXT: brmi .LBB0_2 10; CHECK-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1 11; CHECK-NEXT: lsl r24 12; CHECK-NEXT: dec r22 13; CHECK-NEXT: brpl .LBB0_1 14; CHECK-NEXT: .LBB0_2: 15; CHECK-NEXT: ret 16 %result = shl i8 %a, %b 17 ret i8 %result 18} 19 20; Optimize for size (producing slightly smaller code). 21define i8 @shift_i8_i8_size(i8 %a, i8 %b) optsize { 22; CHECK-LABEL: shift_i8_i8_size: 23; CHECK: ; %bb.0: 24; CHECK-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 25; CHECK-NEXT: dec r22 26; CHECK-NEXT: brmi .LBB1_3 27; CHECK-NEXT: ; %bb.2: ; in Loop: Header=BB1_1 Depth=1 28; CHECK-NEXT: lsl r24 29; CHECK-NEXT: rjmp .LBB1_1 30; CHECK-NEXT: .LBB1_3: 31; CHECK-NEXT: ret 32 %result = shl i8 %a, %b 33 ret i8 %result 34} 35 36define i16 @shift_i16_i16(i16 %a, i16 %b) { 37; CHECK-LABEL: shift_i16_i16: 38; CHECK: ; %bb.0: 39; CHECK-NEXT: dec r22 40; CHECK-NEXT: brmi .LBB2_2 41; CHECK-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1 42; CHECK-NEXT: lsl r24 43; CHECK-NEXT: rol r25 44; CHECK-NEXT: dec r22 45; CHECK-NEXT: brpl .LBB2_1 46; CHECK-NEXT: .LBB2_2: 47; CHECK-NEXT: ret 48 %result = shl i16 %a, %b 49 ret i16 %result 50} 51 52define i64 @shift_i64_i64(i64 %a, i64 %b) { 53; CHECK-LABEL: shift_i64_i64: 54; CHECK: ; %bb.0: 55; CHECK-NEXT: push r16 56; CHECK-NEXT: push r17 57; CHECK-NEXT: mov r30, r10 58; CHECK-NEXT: mov r31, r11 59; CHECK-NEXT: cpi r30, 0 60; CHECK-NEXT: breq .LBB3_3 61; CHECK-NEXT: ; %bb.1: ; %shift.loop.preheader 62; CHECK-NEXT: mov r27, r1 63; CHECK-NEXT: mov r16, r27 64; CHECK-NEXT: mov r17, r27 65; CHECK-NEXT: .LBB3_2: ; %shift.loop 66; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 67; CHECK-NEXT: mov r31, r21 68; CHECK-NEXT: lsl r31 69; CHECK-NEXT: mov r26, r27 70; CHECK-NEXT: rol r26 71; CHECK-NEXT: lsl r22 72; CHECK-NEXT: rol r23 73; CHECK-NEXT: rol r24 74; CHECK-NEXT: rol r25 75; CHECK-NEXT: or r24, r16 76; CHECK-NEXT: or r25, r17 77; CHECK-NEXT: or r22, r26 78; CHECK-NEXT: or r23, r27 79; CHECK-NEXT: lsl r18 80; CHECK-NEXT: rol r19 81; CHECK-NEXT: rol r20 82; CHECK-NEXT: rol r21 83; CHECK-NEXT: dec r30 84; CHECK-NEXT: cpi r30, 0 85; CHECK-NEXT: brne .LBB3_2 86; CHECK-NEXT: .LBB3_3: ; %shift.done 87; CHECK-NEXT: pop r17 88; CHECK-NEXT: pop r16 89; CHECK-NEXT: ret 90 %result = shl i64 %a, %b 91 ret i64 %result 92} 93 94define i8 @lsl_i8_1(i8 %a) { 95; CHECK-LABEL: lsl_i8_1: 96; CHECK: ; %bb.0: 97; CHECK-NEXT: lsl r24 98; CHECK-NEXT: ret 99 %res = shl i8 %a, 1 100 ret i8 %res 101} 102 103define i8 @lsl_i8_2(i8 %a) { 104; CHECK-LABEL: lsl_i8_2: 105; CHECK: ; %bb.0: 106; CHECK-NEXT: lsl r24 107; CHECK-NEXT: lsl r24 108; CHECK-NEXT: ret 109 %res = shl i8 %a, 2 110 ret i8 %res 111} 112 113define i8 @lsl_i8_3(i8 %a) { 114; CHECK-LABEL: lsl_i8_3: 115; CHECK: ; %bb.0: 116; CHECK-NEXT: lsl r24 117; CHECK-NEXT: lsl r24 118; CHECK-NEXT: lsl r24 119; CHECK-NEXT: ret 120 %res = shl i8 %a, 3 121 ret i8 %res 122} 123 124define i8 @lsl_i8_4(i8 %a) { 125; CHECK-LABEL: lsl_i8_4: 126; CHECK: ; %bb.0: 127; CHECK-NEXT: swap r24 128; CHECK-NEXT: andi r24, -16 129; CHECK-NEXT: ret 130 %res = shl i8 %a, 4 131 ret i8 %res 132} 133 134define i8 @lsl_i8_5(i8 %a) { 135; CHECK-LABEL: lsl_i8_5: 136; CHECK: ; %bb.0: 137; CHECK-NEXT: swap r24 138; CHECK-NEXT: andi r24, -16 139; CHECK-NEXT: lsl r24 140; CHECK-NEXT: ret 141 %res = shl i8 %a, 5 142 ret i8 %res 143} 144 145define i8 @lsl_i8_6(i8 %a) { 146; CHECK-LABEL: lsl_i8_6: 147; CHECK: ; %bb.0: 148; CHECK-NEXT: swap r24 149; CHECK-NEXT: andi r24, -16 150; CHECK-NEXT: lsl r24 151; CHECK-NEXT: lsl r24 152; CHECK-NEXT: ret 153 %res = shl i8 %a, 6 154 ret i8 %res 155} 156 157define i8 @lsr_i8_1(i8 %a) { 158; CHECK-LABEL: lsr_i8_1: 159; CHECK: ; %bb.0: 160; CHECK-NEXT: lsr r24 161; CHECK-NEXT: ret 162 %res = lshr i8 %a, 1 163 ret i8 %res 164} 165 166define i8 @lsr_i8_2(i8 %a) { 167; CHECK-LABEL: lsr_i8_2: 168; CHECK: ; %bb.0: 169; CHECK-NEXT: lsr r24 170; CHECK-NEXT: lsr r24 171; CHECK-NEXT: ret 172 %res = lshr i8 %a, 2 173 ret i8 %res 174} 175 176define i8 @lsr_i8_3(i8 %a) { 177; CHECK-LABEL: lsr_i8_3: 178; CHECK: ; %bb.0: 179; CHECK-NEXT: lsr r24 180; CHECK-NEXT: lsr r24 181; CHECK-NEXT: lsr r24 182; CHECK-NEXT: ret 183 %res = lshr i8 %a, 3 184 ret i8 %res 185} 186 187define i8 @lsr_i8_4(i8 %a) { 188; CHECK-LABEL: lsr_i8_4: 189; CHECK: ; %bb.0: 190; CHECK-NEXT: swap r24 191; CHECK-NEXT: andi r24, 15 192; CHECK-NEXT: ret 193 %res = lshr i8 %a, 4 194 ret i8 %res 195} 196 197define i8 @lsr_i8_5(i8 %a) { 198; CHECK-LABEL: lsr_i8_5: 199; CHECK: ; %bb.0: 200; CHECK-NEXT: swap r24 201; CHECK-NEXT: andi r24, 15 202; CHECK-NEXT: lsr r24 203; CHECK-NEXT: ret 204 %res = lshr i8 %a, 5 205 ret i8 %res 206} 207 208define i8 @lsr_i8_6(i8 %a) { 209; CHECK-LABEL: lsr_i8_6: 210; CHECK: ; %bb.0: 211; CHECK-NEXT: swap r24 212; CHECK-NEXT: andi r24, 15 213; CHECK-NEXT: lsr r24 214; CHECK-NEXT: lsr r24 215; CHECK-NEXT: ret 216 %res = lshr i8 %a, 6 217 ret i8 %res 218} 219 220define i8 @lsl_i8_7(i8 %a) { 221; CHECK-LABEL: lsl_i8_7: 222; CHECK: ; %bb.0: 223; CHECK-NEXT: ror r24 224; CHECK-NEXT: clr r24 225; CHECK-NEXT: ror r24 226; CHECK-NEXT: ret 227 %result = shl i8 %a, 7 228 ret i8 %result 229} 230 231define i8 @lsr_i8_7(i8 %a) { 232; CHECK-LABEL: lsr_i8_7: 233; CHECK: ; %bb.0: 234; CHECK-NEXT: rol r24 235; CHECK-NEXT: clr r24 236; CHECK-NEXT: rol r24 237; CHECK-NEXT: ret 238 %result = lshr i8 %a, 7 239 ret i8 %result 240} 241 242define i8 @asr_i8_6(i8 %a) { 243; CHECK-LABEL: asr_i8_6: 244; CHECK: ; %bb.0: 245; CHECK-NEXT: bst r24, 6 246; CHECK-NEXT: lsl r24 247; CHECK-NEXT: sbc r24, r24 248; CHECK-NEXT: bld r24, 0 249; CHECK-NEXT: ret 250 %result = ashr i8 %a, 6 251 ret i8 %result 252} 253 254define i8 @asr_i8_7(i8 %a) { 255; CHECK-LABEL: asr_i8_7: 256; CHECK: ; %bb.0: 257; CHECK-NEXT: lsl r24 258; CHECK-NEXT: sbc r24, r24 259; CHECK-NEXT: ret 260 %result = ashr i8 %a, 7 261 ret i8 %result 262} 263 264define i16 @lsl_i16_5(i16 %a) { 265; CHECK-LABEL: lsl_i16_5: 266; CHECK: ; %bb.0: 267; CHECK-NEXT: swap r25 268; CHECK-NEXT: swap r24 269; CHECK-NEXT: andi r25, 240 270; CHECK-NEXT: eor r25, r24 271; CHECK-NEXT: andi r24, 240 272; CHECK-NEXT: eor r25, r24 273; CHECK-NEXT: lsl r24 274; CHECK-NEXT: rol r25 275; CHECK-NEXT: ret 276 %result = shl i16 %a, 5 277 ret i16 %result 278} 279 280define i16 @lsl_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) { 281; CHECK-LABEL: lsl_i16_6: 282; CHECK: ; %bb.0: 283; CHECK-NEXT: mov r24, r14 284; CHECK-NEXT: mov r25, r15 285; CHECK-NEXT: swap r25 286; CHECK-NEXT: swap r24 287; CHECK-NEXT: andi r25, 240 288; CHECK-NEXT: eor r25, r24 289; CHECK-NEXT: andi r24, 240 290; CHECK-NEXT: eor r25, r24 291; CHECK-NEXT: lsl r24 292; CHECK-NEXT: rol r25 293; CHECK-NEXT: lsl r24 294; CHECK-NEXT: rol r25 295; CHECK-NEXT: ret 296 %result = shl i16 %f, 6 297 ret i16 %result 298} 299 300define i16 @lsl_i16_9(i16 %a) { 301; CHECK-LABEL: lsl_i16_9: 302; CHECK: ; %bb.0: 303; CHECK-NEXT: mov r25, r24 304; CHECK-NEXT: clr r24 305; CHECK-NEXT: lsl r25 306; CHECK-NEXT: ret 307 %result = shl i16 %a, 9 308 ret i16 %result 309} 310 311define i16 @lsl_i16_13(i16 %a) { 312; CHECK-LABEL: lsl_i16_13: 313; CHECK: ; %bb.0: 314; CHECK-NEXT: mov r25, r24 315; CHECK-NEXT: swap r25 316; CHECK-NEXT: andi r25, 240 317; CHECK-NEXT: clr r24 318; CHECK-NEXT: lsl r25 319; CHECK-NEXT: ret 320 %result = shl i16 %a, 13 321 ret i16 %result 322} 323 324define i16 @lsr_i16_5(i16 %a) { 325; CHECK-LABEL: lsr_i16_5: 326; CHECK: ; %bb.0: 327; CHECK-NEXT: swap r25 328; CHECK-NEXT: swap r24 329; CHECK-NEXT: andi r24, 15 330; CHECK-NEXT: eor r24, r25 331; CHECK-NEXT: andi r25, 15 332; CHECK-NEXT: eor r24, r25 333; CHECK-NEXT: lsr r25 334; CHECK-NEXT: ror r24 335; CHECK-NEXT: ret 336 %result = lshr i16 %a, 5 337 ret i16 %result 338} 339 340define i16 @lsr_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) { 341; CHECK-LABEL: lsr_i16_6: 342; CHECK: ; %bb.0: 343; CHECK-NEXT: mov r24, r14 344; CHECK-NEXT: mov r25, r15 345; CHECK-NEXT: swap r25 346; CHECK-NEXT: swap r24 347; CHECK-NEXT: andi r24, 15 348; CHECK-NEXT: eor r24, r25 349; CHECK-NEXT: andi r25, 15 350; CHECK-NEXT: eor r24, r25 351; CHECK-NEXT: lsr r25 352; CHECK-NEXT: ror r24 353; CHECK-NEXT: lsr r25 354; CHECK-NEXT: ror r24 355; CHECK-NEXT: ret 356 %result = lshr i16 %f, 6 357 ret i16 %result 358} 359 360define i16 @lsr_i16_9(i16 %a) { 361; CHECK-LABEL: lsr_i16_9: 362; CHECK: ; %bb.0: 363; CHECK-NEXT: mov r24, r25 364; CHECK-NEXT: clr r25 365; CHECK-NEXT: lsr r24 366; CHECK-NEXT: ret 367 %result = lshr i16 %a, 9 368 ret i16 %result 369} 370 371define i16 @lsr_i16_13(i16 %a) { 372; CHECK-LABEL: lsr_i16_13: 373; CHECK: ; %bb.0: 374; CHECK-NEXT: mov r24, r25 375; CHECK-NEXT: swap r24 376; CHECK-NEXT: andi r24, 15 377; CHECK-NEXT: clr r25 378; CHECK-NEXT: lsr r24 379; CHECK-NEXT: ret 380 %result = lshr i16 %a, 13 381 ret i16 %result 382} 383 384define i16 @asr_i16_7(i16 %a) { 385; CHECK-LABEL: asr_i16_7: 386; CHECK: ; %bb.0: 387; CHECK-NEXT: lsl r24 388; CHECK-NEXT: mov r24, r25 389; CHECK-NEXT: rol r24 390; CHECK-NEXT: sbc r25, r25 391; CHECK-NEXT: ret 392 %result = ashr i16 %a, 7 393 ret i16 %result 394} 395 396define i16 @asr_i16_9(i16 %a) { 397; CHECK-LABEL: asr_i16_9: 398; CHECK: ; %bb.0: 399; CHECK-NEXT: mov r24, r25 400; CHECK-NEXT: lsl r25 401; CHECK-NEXT: sbc r25, r25 402; CHECK-NEXT: asr r24 403; CHECK-NEXT: ret 404 %result = ashr i16 %a, 9 405 ret i16 %result 406} 407 408define i16 @asr_i16_12(i16 %a) { 409; CHECK-LABEL: asr_i16_12: 410; CHECK: ; %bb.0: 411; CHECK-NEXT: mov r24, r25 412; CHECK-NEXT: lsl r25 413; CHECK-NEXT: sbc r25, r25 414; CHECK-NEXT: asr r24 415; CHECK-NEXT: asr r24 416; CHECK-NEXT: asr r24 417; CHECK-NEXT: asr r24 418; CHECK-NEXT: ret 419 %result = ashr i16 %a, 12 420 ret i16 %result 421} 422 423define i16 @asr_i16_14(i16 %a) { 424; CHECK-LABEL: asr_i16_14: 425; CHECK: ; %bb.0: 426; CHECK-NEXT: lsl r25 427; CHECK-NEXT: sbc r24, r24 428; CHECK-NEXT: lsl r25 429; CHECK-NEXT: mov r25, r24 430; CHECK-NEXT: rol r24 431; CHECK-NEXT: ret 432 %result = ashr i16 %a, 14 433 ret i16 %result 434} 435 436define i16 @asr_i16_15(i16 %a) { 437; CHECK-LABEL: asr_i16_15: 438; CHECK: ; %bb.0: 439; CHECK-NEXT: lsl r25 440; CHECK-NEXT: sbc r25, r25 441; CHECK-NEXT: mov r24, r25 442; CHECK-NEXT: ret 443 %result = ashr i16 %a, 15 444 ret i16 %result 445} 446