xref: /llvm-project/llvm/test/CodeGen/AVR/rotate.ll (revision 71d90f310867c78532c5bdb9ba553859910ee67e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=avr | FileCheck %s
3
4define i8 @rotl8_1(i8 %x) {
5; CHECK-LABEL: rotl8_1:
6; CHECK:       ; %bb.0: ; %start
7; CHECK-NEXT:    lsl r24
8; CHECK-NEXT:    adc r24, r1
9; CHECK-NEXT:    ret
10start:
11  %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 1)
12  ret i8 %0
13}
14
15define i8 @rotl8_3(i8 %x) {
16; CHECK-LABEL: rotl8_3:
17; CHECK:       ; %bb.0: ; %start
18; CHECK-NEXT:    swap r24
19; CHECK-NEXT:    bst r24, 0
20; CHECK-NEXT:    ror r24
21; CHECK-NEXT:    bld r24, 7
22; CHECK-NEXT:    ret
23start:
24  %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
25  ret i8 %0
26}
27
28define i8 @rotl8_5(i8 %x) {
29; CHECK-LABEL: rotl8_5:
30; CHECK:       ; %bb.0: ; %start
31; CHECK-NEXT:    swap r24
32; CHECK-NEXT:    lsl r24
33; CHECK-NEXT:    adc r24, r1
34; CHECK-NEXT:    ret
35start:
36  %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 5)
37  ret i8 %0
38}
39
40define i8 @rotl8_7(i8 %x) {
41; CHECK-LABEL: rotl8_7:
42; CHECK:       ; %bb.0: ; %start
43; CHECK-NEXT:    bst r24, 0
44; CHECK-NEXT:    ror r24
45; CHECK-NEXT:    bld r24, 7
46; CHECK-NEXT:    ret
47start:
48  %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 7)
49  ret i8 %0
50}
51
52define i8 @rotl8_dyn(i8 %x, i8 %y) {
53; CHECK-LABEL: rotl8_dyn:
54; CHECK:       ; %bb.0: ; %start
55; CHECK-NEXT:    andi r22, 7
56; CHECK-NEXT:    dec r22
57; CHECK-NEXT:    brmi .LBB4_2
58; CHECK-NEXT:  .LBB4_1: ; %start
59; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
60; CHECK-NEXT:    lsl r24
61; CHECK-NEXT:    adc r24, r1
62; CHECK-NEXT:    dec r22
63; CHECK-NEXT:    brpl .LBB4_1
64; CHECK-NEXT:  .LBB4_2: ; %start
65; CHECK-NEXT:    ret
66start:
67  %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
68  ret i8 %0
69}
70
71define i8 @rotr8_1(i8 %x) {
72; CHECK-LABEL: rotr8_1:
73; CHECK:       ; %bb.0: ; %start
74; CHECK-NEXT:    bst r24, 0
75; CHECK-NEXT:    ror r24
76; CHECK-NEXT:    bld r24, 7
77; CHECK-NEXT:    ret
78start:
79  %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 1)
80  ret i8 %0
81}
82
83define i8 @rotr8_3(i8 %x) {
84; CHECK-LABEL: rotr8_3:
85; CHECK:       ; %bb.0: ; %start
86; CHECK-NEXT:    swap r24
87; CHECK-NEXT:    lsl r24
88; CHECK-NEXT:    adc r24, r1
89; CHECK-NEXT:    ret
90start:
91  %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
92  ret i8 %0
93}
94
95define i8 @rotr8_5(i8 %x) {
96; CHECK-LABEL: rotr8_5:
97; CHECK:       ; %bb.0: ; %start
98; CHECK-NEXT:    swap r24
99; CHECK-NEXT:    bst r24, 0
100; CHECK-NEXT:    ror r24
101; CHECK-NEXT:    bld r24, 7
102; CHECK-NEXT:    ret
103start:
104  %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 5)
105  ret i8 %0
106}
107
108define i8 @rotr8_7(i8 %x) {
109; CHECK-LABEL: rotr8_7:
110; CHECK:       ; %bb.0: ; %start
111; CHECK-NEXT:    lsl r24
112; CHECK-NEXT:    adc r24, r1
113; CHECK-NEXT:    ret
114start:
115  %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 7)
116  ret i8 %0
117}
118
119define i8 @rotr8_dyn(i8 %x, i8 %y) {
120; CHECK-LABEL: rotr8_dyn:
121; CHECK:       ; %bb.0: ; %start
122; CHECK-NEXT:    andi r22, 7
123; CHECK-NEXT:    dec r22
124; CHECK-NEXT:    brmi .LBB9_2
125; CHECK-NEXT:  .LBB9_1: ; %start
126; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
127; CHECK-NEXT:    bst r24, 0
128; CHECK-NEXT:    ror r24
129; CHECK-NEXT:    bld r24, 7
130; CHECK-NEXT:    dec r22
131; CHECK-NEXT:    brpl .LBB9_1
132; CHECK-NEXT:  .LBB9_2: ; %start
133; CHECK-NEXT:    ret
134start:
135  %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
136  ret i8 %0
137}
138
139define i16 @rotl16(i16 %x) {
140; CHECK-LABEL: rotl16:
141; CHECK:       ; %bb.0: ; %start
142; CHECK-NEXT:    mov r18, r24
143; CHECK-NEXT:    mov r19, r25
144; CHECK-NEXT:    lsl r18
145; CHECK-NEXT:    rol r19
146; CHECK-NEXT:    lsl r18
147; CHECK-NEXT:    rol r19
148; CHECK-NEXT:    mov r24, r25
149; CHECK-NEXT:    swap r24
150; CHECK-NEXT:    andi r24, 15
151; CHECK-NEXT:    clr r25
152; CHECK-NEXT:    lsr r24
153; CHECK-NEXT:    lsr r24
154; CHECK-NEXT:    or r24, r18
155; CHECK-NEXT:    or r25, r19
156; CHECK-NEXT:    ret
157start:
158  %0 = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 2)
159  ret i16 %0
160}
161
162define i16 @rotr16(i16 %x) {
163; CHECK-LABEL: rotr16:
164; CHECK:       ; %bb.0: ; %start
165; CHECK-NEXT:    mov r18, r24
166; CHECK-NEXT:    mov r19, r25
167; CHECK-NEXT:    lsr r19
168; CHECK-NEXT:    ror r18
169; CHECK-NEXT:    lsr r19
170; CHECK-NEXT:    ror r18
171; CHECK-NEXT:    mov r25, r24
172; CHECK-NEXT:    swap r25
173; CHECK-NEXT:    andi r25, 240
174; CHECK-NEXT:    clr r24
175; CHECK-NEXT:    lsl r25
176; CHECK-NEXT:    lsl r25
177; CHECK-NEXT:    or r24, r18
178; CHECK-NEXT:    or r25, r19
179; CHECK-NEXT:    ret
180start:
181  %0 = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 2)
182  ret i16 %0
183}
184
185define i32 @rotl32(i32 %x) {
186; CHECK-LABEL: rotl32:
187; CHECK:       ; %bb.0: ; %start
188; CHECK-NEXT:    mov r20, r22
189; CHECK-NEXT:    mov r21, r23
190; CHECK-NEXT:    lsl r20
191; CHECK-NEXT:    rol r21
192; CHECK-NEXT:    lsl r20
193; CHECK-NEXT:    rol r21
194; CHECK-NEXT:    mov r18, r24
195; CHECK-NEXT:    mov r19, r25
196; CHECK-NEXT:    mov r18, r19
197; CHECK-NEXT:    swap r18
198; CHECK-NEXT:    andi r18, 15
199; CHECK-NEXT:    clr r19
200; CHECK-NEXT:    lsr r18
201; CHECK-NEXT:    lsr r18
202; CHECK-NEXT:    or r18, r20
203; CHECK-NEXT:    or r19, r21
204; CHECK-NEXT:    lsl r24
205; CHECK-NEXT:    rol r25
206; CHECK-NEXT:    lsl r24
207; CHECK-NEXT:    rol r25
208; CHECK-NEXT:    mov r22, r23
209; CHECK-NEXT:    swap r22
210; CHECK-NEXT:    andi r22, 15
211; CHECK-NEXT:    clr r23
212; CHECK-NEXT:    lsr r22
213; CHECK-NEXT:    lsr r22
214; CHECK-NEXT:    or r24, r22
215; CHECK-NEXT:    or r25, r23
216; CHECK-NEXT:    mov r22, r18
217; CHECK-NEXT:    mov r23, r19
218; CHECK-NEXT:    ret
219start:
220  %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 2)
221  ret i32 %0
222}
223
224define i32 @rotr32(i32 %x) {
225; CHECK-LABEL: rotr32:
226; CHECK:       ; %bb.0: ; %start
227; CHECK-NEXT:    mov r20, r22
228; CHECK-NEXT:    mov r21, r23
229; CHECK-NEXT:    lsr r21
230; CHECK-NEXT:    ror r20
231; CHECK-NEXT:    lsr r21
232; CHECK-NEXT:    ror r20
233; CHECK-NEXT:    mov r18, r24
234; CHECK-NEXT:    mov r19, r25
235; CHECK-NEXT:    mov r19, r18
236; CHECK-NEXT:    swap r19
237; CHECK-NEXT:    andi r19, 240
238; CHECK-NEXT:    clr r18
239; CHECK-NEXT:    lsl r19
240; CHECK-NEXT:    lsl r19
241; CHECK-NEXT:    or r18, r20
242; CHECK-NEXT:    or r19, r21
243; CHECK-NEXT:    lsr r25
244; CHECK-NEXT:    ror r24
245; CHECK-NEXT:    lsr r25
246; CHECK-NEXT:    ror r24
247; CHECK-NEXT:    mov r23, r22
248; CHECK-NEXT:    swap r23
249; CHECK-NEXT:    andi r23, 240
250; CHECK-NEXT:    clr r22
251; CHECK-NEXT:    lsl r23
252; CHECK-NEXT:    lsl r23
253; CHECK-NEXT:    or r24, r22
254; CHECK-NEXT:    or r25, r23
255; CHECK-NEXT:    mov r22, r18
256; CHECK-NEXT:    mov r23, r19
257; CHECK-NEXT:    ret
258start:
259  %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 2)
260  ret i32 %0
261}
262
263declare i8 @llvm.fshl.i8(i8, i8, i8)
264declare i8 @llvm.fshr.i8(i8, i8, i8)
265
266declare i16 @llvm.fshl.i16(i16, i16, i16)
267declare i16 @llvm.fshr.i16(i16, i16, i16)
268
269declare i32 @llvm.fshl.i32(i32, i32, i32)
270declare i32 @llvm.fshr.i32(i32, i32, i32)
271