1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s 3 4define signext i16 @testmsws(float %x) { 5; CHECK-LABEL: testmsws: 6; CHECK: ; %bb.0: ; %entry 7; CHECK-NEXT: call lroundf 8; CHECK-NEXT: movw r24, r22 9; CHECK-NEXT: ret 10entry: 11 %0 = tail call i32 @llvm.lround.i32.f32(float %x) 12 %conv = trunc i32 %0 to i16 13 ret i16 %conv 14} 15 16define i32 @testmsxs(float %x) { 17; CHECK-LABEL: testmsxs: 18; CHECK: ; %bb.0: ; %entry 19; CHECK-NEXT: call lroundf 20; CHECK-NEXT: ret 21entry: 22 %0 = tail call i32 @llvm.lround.i32.f32(float %x) 23 ret i32 %0 24} 25 26define signext i16 @testmswd(double %x) { 27; CHECK-LABEL: testmswd: 28; CHECK: ; %bb.0: ; %entry 29; CHECK-NEXT: call lround 30; CHECK-NEXT: movw r24, r22 31; CHECK-NEXT: ret 32entry: 33 %0 = tail call i32 @llvm.lround.i32.f64(double %x) 34 %conv = trunc i32 %0 to i16 35 ret i16 %conv 36} 37 38define i32 @testmsxd(double %x) { 39; CHECK-LABEL: testmsxd: 40; CHECK: ; %bb.0: ; %entry 41; CHECK-NEXT: call lround 42; CHECK-NEXT: ret 43entry: 44 %0 = tail call i32 @llvm.lround.i32.f64(double %x) 45 ret i32 %0 46} 47 48declare i32 @llvm.lround.i32.f32(float) nounwind readnone 49declare i32 @llvm.lround.i32.f64(double) nounwind readnone 50