1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s 3 4define signext i32 @testmsws(float %x) { 5; CHECK-LABEL: testmsws: 6; CHECK: ; %bb.0: ; %entry 7; CHECK-NEXT: call llroundf 8; CHECK-NEXT: movw r22, r18 9; CHECK-NEXT: movw r24, r20 10; CHECK-NEXT: ret 11entry: 12 %0 = tail call i64 @llvm.llround.i64.f32(float %x) 13 %conv = trunc i64 %0 to i32 14 ret i32 %conv 15} 16 17define i64 @testmsxs(float %x) { 18; CHECK-LABEL: testmsxs: 19; CHECK: ; %bb.0: ; %entry 20; CHECK-NEXT: call llroundf 21; CHECK-NEXT: ret 22entry: 23 %0 = tail call i64 @llvm.llround.i64.f32(float %x) 24 ret i64 %0 25} 26 27define signext i32 @testmswd(double %x) { 28; CHECK-LABEL: testmswd: 29; CHECK: ; %bb.0: ; %entry 30; CHECK-NEXT: call llround 31; CHECK-NEXT: movw r22, r18 32; CHECK-NEXT: movw r24, r20 33; CHECK-NEXT: ret 34entry: 35 %0 = tail call i64 @llvm.llround.i64.f64(double %x) 36 %conv = trunc i64 %0 to i32 37 ret i32 %conv 38} 39 40define i64 @testmsxd(double %x) { 41; CHECK-LABEL: testmsxd: 42; CHECK: ; %bb.0: ; %entry 43; CHECK-NEXT: call llround 44; CHECK-NEXT: ret 45entry: 46 %0 = tail call i64 @llvm.llround.i64.f64(double %x) 47 ret i64 %0 48} 49 50declare i64 @llvm.llround.i64.f32(float) nounwind readnone 51declare i64 @llvm.llround.i64.f64(double) nounwind readnone 52