13b8c12c1SBen Shi; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 23b8c12c1SBen Shi; RUN: llc -mattr=mul,movw < %s -mtriple=avr | FileCheck %s 37203e00bSDylan McKay 47203e00bSDylan McKay; Tests lowering of multiplication to hardware instructions. 57203e00bSDylan McKay 67203e00bSDylan McKaydefine i8 @mult8(i8 %a, i8 %b) { 77203e00bSDylan McKay; CHECK-LABEL: mult8: 83b8c12c1SBen Shi; CHECK: ; %bb.0: 93b8c12c1SBen Shi; CHECK-NEXT: muls r22, r24 103b8c12c1SBen Shi; CHECK-NEXT: clr r1 113b8c12c1SBen Shi; CHECK-NEXT: mov r24, r0 123b8c12c1SBen Shi; CHECK-NEXT: ret 137203e00bSDylan McKay %mul = mul i8 %b, %a 147203e00bSDylan McKay ret i8 %mul 157203e00bSDylan McKay} 167203e00bSDylan McKay 177203e00bSDylan McKaydefine i16 @mult16(i16 %a, i16 %b) { 187203e00bSDylan McKay; CHECK-LABEL: mult16: 193b8c12c1SBen Shi; CHECK: ; %bb.0: 203b8c12c1SBen Shi; CHECK-NEXT: muls r22, r25 21cef723a0SBen Shi; CHECK-NEXT: mov r25, r0 223b8c12c1SBen Shi; CHECK-NEXT: clr r1 233b8c12c1SBen Shi; CHECK-NEXT: mul r22, r24 24*7b3bbd83SJay Foad; CHECK-NEXT: mov r20, r0 25*7b3bbd83SJay Foad; CHECK-NEXT: mov r18, r1 263b8c12c1SBen Shi; CHECK-NEXT: clr r1 27*7b3bbd83SJay Foad; CHECK-NEXT: add r18, r25 283b8c12c1SBen Shi; CHECK-NEXT: muls r23, r24 293b8c12c1SBen Shi; CHECK-NEXT: clr r1 30*7b3bbd83SJay Foad; CHECK-NEXT: add r18, r0 31*7b3bbd83SJay Foad; CHECK-NEXT: mov r19, r18 32*7b3bbd83SJay Foad; CHECK-NEXT: clr r18 33*7b3bbd83SJay Foad; CHECK-NEXT: mov r24, r20 343b8c12c1SBen Shi; CHECK-NEXT: clr r25 35*7b3bbd83SJay Foad; CHECK-NEXT: or r24, r18 36*7b3bbd83SJay Foad; CHECK-NEXT: or r25, r19 373b8c12c1SBen Shi; CHECK-NEXT: ret 387203e00bSDylan McKay %mul = mul nsw i16 %b, %a 397203e00bSDylan McKay ret i16 %mul 407203e00bSDylan McKay} 41