xref: /llvm-project/llvm/test/CodeGen/AVR/hardware-mul.ll (revision 7b3bbd83c0c24087072ec5b22a76799ab31f87d5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mattr=mul,movw < %s -mtriple=avr | FileCheck %s
3
4; Tests lowering of multiplication to hardware instructions.
5
6define i8 @mult8(i8 %a, i8 %b) {
7; CHECK-LABEL: mult8:
8; CHECK:       ; %bb.0:
9; CHECK-NEXT:    muls r22, r24
10; CHECK-NEXT:    clr r1
11; CHECK-NEXT:    mov r24, r0
12; CHECK-NEXT:    ret
13  %mul = mul i8 %b, %a
14  ret i8 %mul
15}
16
17define i16 @mult16(i16 %a, i16 %b) {
18; CHECK-LABEL: mult16:
19; CHECK:       ; %bb.0:
20; CHECK-NEXT:    muls r22, r25
21; CHECK-NEXT:    mov r25, r0
22; CHECK-NEXT:    clr r1
23; CHECK-NEXT:    mul r22, r24
24; CHECK-NEXT:    mov r20, r0
25; CHECK-NEXT:    mov r18, r1
26; CHECK-NEXT:    clr r1
27; CHECK-NEXT:    add r18, r25
28; CHECK-NEXT:    muls r23, r24
29; CHECK-NEXT:    clr r1
30; CHECK-NEXT:    add r18, r0
31; CHECK-NEXT:    mov r19, r18
32; CHECK-NEXT:    clr r18
33; CHECK-NEXT:    mov r24, r20
34; CHECK-NEXT:    clr r25
35; CHECK-NEXT:    or r24, r18
36; CHECK-NEXT:    or r25, r19
37; CHECK-NEXT:    ret
38  %mul = mul nsw i16 %b, %a
39  ret i16 %mul
40}
41