1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc < %s -mtriple=avr -mcpu=atmega328 -O1 -verify-machineinstrs | FileCheck %s 3 4define internal i8 @main() { 5; CHECK-LABEL: main: 6; CHECK: ; %bb.0: ; %bb0 7; CHECK-NEXT: push r2 8; CHECK-NEXT: push r3 9; CHECK-NEXT: push r4 10; CHECK-NEXT: push r5 11; CHECK-NEXT: push r6 12; CHECK-NEXT: push r7 13; CHECK-NEXT: push r8 14; CHECK-NEXT: push r9 15; CHECK-NEXT: push r10 16; CHECK-NEXT: push r11 17; CHECK-NEXT: push r12 18; CHECK-NEXT: push r13 19; CHECK-NEXT: push r14 20; CHECK-NEXT: push r15 21; CHECK-NEXT: push r16 22; CHECK-NEXT: push r17 23; CHECK-NEXT: push r28 24; CHECK-NEXT: push r29 25; CHECK-NEXT: in r28, 61 26; CHECK-NEXT: in r29, 62 27; CHECK-NEXT: sbiw r28, 13 28; CHECK-NEXT: in r0, 63 29; CHECK-NEXT: cli 30; CHECK-NEXT: out 62, r29 31; CHECK-NEXT: out 63, r0 32; CHECK-NEXT: out 61, r28 33; CHECK-NEXT: ldi r16, 0 34; CHECK-NEXT: ldi r17, 0 35; CHECK-NEXT: ldi r18, -1 36; CHECK-NEXT: ;APP 37; CHECK-NEXT: ldi r24, 123 38; CHECK-NEXT: ;NO_APP 39; CHECK-NEXT: std Y+1, r24 ; 1-byte Folded Spill 40; CHECK-NEXT: movw r24, r28 41; CHECK-NEXT: adiw r24, 6 42; CHECK-NEXT: std Y+3, r25 ; 2-byte Folded Spill 43; CHECK-NEXT: std Y+2, r24 ; 2-byte Folded Spill 44; CHECK-NEXT: movw r8, r16 45; CHECK-NEXT: movw r6, r16 46; CHECK-NEXT: movw r4, r16 47; CHECK-NEXT: movw r2, r16 48; CHECK-NEXT: rjmp .LBB0_2 49; CHECK-NEXT: .LBB0_1: ; %bb1 50; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1 51; CHECK-NEXT: andi r30, 1 52; CHECK-NEXT: ldd r31, Y+4 ; 1-byte Folded Reload 53; CHECK-NEXT: dec r31 54; CHECK-NEXT: cpi r30, 0 55; CHECK-NEXT: movw r8, r18 56; CHECK-NEXT: movw r6, r20 57; CHECK-NEXT: movw r4, r22 58; CHECK-NEXT: movw r2, r24 59; CHECK-NEXT: mov r18, r31 60; CHECK-NEXT: brne .LBB0_2 61; CHECK-NEXT: rjmp .LBB0_4 62; CHECK-NEXT: .LBB0_2: ; %bb1 63; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 64; CHECK-NEXT: std Y+4, r18 ; 1-byte Folded Spill 65; CHECK-NEXT: movw r18, r8 66; CHECK-NEXT: movw r20, r6 67; CHECK-NEXT: movw r22, r4 68; CHECK-NEXT: movw r24, r2 69; CHECK-NEXT: ldi r26, 10 70; CHECK-NEXT: ldi r27, 0 71; CHECK-NEXT: movw r10, r26 72; CHECK-NEXT: movw r12, r16 73; CHECK-NEXT: movw r14, r16 74; CHECK-NEXT: call __udivdi3 75; CHECK-NEXT: std Y+13, r25 76; CHECK-NEXT: std Y+12, r24 77; CHECK-NEXT: std Y+11, r23 78; CHECK-NEXT: std Y+10, r22 79; CHECK-NEXT: std Y+9, r21 80; CHECK-NEXT: std Y+8, r20 81; CHECK-NEXT: std Y+7, r19 82; CHECK-NEXT: std Y+6, r18 83; CHECK-NEXT: ldd r30, Y+2 ; 2-byte Folded Reload 84; CHECK-NEXT: ldd r31, Y+3 ; 2-byte Folded Reload 85; CHECK-NEXT: ;APP 86; CHECK-NEXT: ;NO_APP 87; CHECK-NEXT: ldi r30, 1 88; CHECK-NEXT: cp r8, r1 89; CHECK-NEXT: cpc r9, r1 90; CHECK-NEXT: cpc r6, r16 91; CHECK-NEXT: cpc r7, r17 92; CHECK-NEXT: cpc r4, r16 93; CHECK-NEXT: cpc r5, r17 94; CHECK-NEXT: cpc r2, r16 95; CHECK-NEXT: cpc r3, r17 96; CHECK-NEXT: breq .LBB0_3 97; CHECK-NEXT: rjmp .LBB0_1 98; CHECK-NEXT: .LBB0_3: ; %bb1 99; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1 100; CHECK-NEXT: mov r30, r1 101; CHECK-NEXT: rjmp .LBB0_1 102; CHECK-NEXT: .LBB0_4: ; %bb3 103; CHECK-NEXT: ldd r24, Y+1 ; 1-byte Folded Reload 104; CHECK-NEXT: std Y+5, r24 105; CHECK-NEXT: movw r24, r28 106; CHECK-NEXT: adiw r24, 5 107; CHECK-NEXT: ;APP 108; CHECK-NEXT: ;NO_APP 109; CHECK-NEXT: ldd r24, Y+5 110; CHECK-NEXT: adiw r28, 13 111; CHECK-NEXT: in r0, 63 112; CHECK-NEXT: cli 113; CHECK-NEXT: out 62, r29 114; CHECK-NEXT: out 63, r0 115; CHECK-NEXT: out 61, r28 116; CHECK-NEXT: pop r29 117; CHECK-NEXT: pop r28 118; CHECK-NEXT: pop r17 119; CHECK-NEXT: pop r16 120; CHECK-NEXT: pop r15 121; CHECK-NEXT: pop r14 122; CHECK-NEXT: pop r13 123; CHECK-NEXT: pop r12 124; CHECK-NEXT: pop r11 125; CHECK-NEXT: pop r10 126; CHECK-NEXT: pop r9 127; CHECK-NEXT: pop r8 128; CHECK-NEXT: pop r7 129; CHECK-NEXT: pop r6 130; CHECK-NEXT: pop r5 131; CHECK-NEXT: pop r4 132; CHECK-NEXT: pop r3 133; CHECK-NEXT: pop r2 134; CHECK-NEXT: ret 135bb0: 136 %0 = alloca i64 137 %1 = alloca i8 138 %2 = tail call i8 asm sideeffect "ldi ${0}, 123", "=&r,~{sreg},~{memory}"() 139 140 br label %bb1 141 142bb1: 143 %3 = phi i64 [ %5, %bb1 ], [ 0, %bb0 ] 144 %4 = phi i8 [ %6, %bb1 ], [ 0, %bb0 ] 145 %5 = udiv i64 %3, 10 146 %6 = add i8 %4, 1 147 148 store i64 %5, ptr %0 149 call void asm sideeffect "", "r,~{memory}"(ptr %0) 150 151 %7 = icmp eq i64 %3, 0 152 %8 = icmp eq i8 %6, 0 153 154 br i1 %7, label %bb3, label %bb1 155 156bb3: 157 store i8 %2, ptr %1 158 call void asm sideeffect "", "r,~{memory}"(ptr %1) 159 160 %9 = load i8, ptr %1 161 162 ret i8 %9 163} 164