xref: /llvm-project/llvm/test/CodeGen/AVR/add.ll (revision 9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3) 
1; RUN: llc -mattr=addsubiw < %s -mtriple=avr | FileCheck %s
2
3define i8 @add8_reg_reg(i8 %a, i8 %b) {
4; CHECK-LABEL: add8_reg_reg:
5; CHECK: add r24, r22
6    %result = add i8 %a, %b
7    ret i8 %result
8}
9
10define i8 @add8_reg_imm(i8 %a) {
11; CHECK-LABEL: add8_reg_imm:
12; CHECK: subi r24, -5
13    %result = add i8 %a, 5
14    ret i8 %result
15}
16
17define i8 @add8_reg_increment(i8 %a) {
18; CHECK-LABEL: add8_reg_increment:
19; CHECK: inc r24
20    %result = add i8 %a, 1
21    ret i8 %result
22}
23
24
25define i16 @add16_reg_reg(i16 %a, i16 %b) {
26; CHECK-LABEL: add16_reg_reg:
27; CHECK: add r24, r22
28; CHECK: adc r25, r23
29    %result = add i16 %a, %b
30    ret i16 %result
31}
32
33define i16 @add16_reg_imm(i16 %a) {
34; CHECK-LABEL: add16_reg_imm:
35; CHECK: adiw r24, 63
36    %result = add i16 %a, 63
37    ret i16 %result
38}
39
40define i16 @add16_reg_imm_subi(i16 %a) {
41; CHECK-LABEL: add16_reg_imm_subi:
42; CHECK: subi r24, 133
43; CHECK: sbci r25, 255
44    %result = add i16 %a, 123
45    ret i16 %result
46}
47
48define i16 @add16_reg_reg_zext(i16 %a, i1 zeroext %b) {
49; CHECK-LABEL: add16_reg_reg_zext:
50; CHECK: mov r18, r22
51; CHECK: clr r19
52; CHECK: add r24, r18
53; CHECK: adc r25, r19
54    %zext = zext i1 %b to i16
55    %result = add i16 %a, %zext
56    ret i16 %result
57}
58
59define i32 @add32_reg_reg(i32 %a, i32 %b) {
60; CHECK-LABEL: add32_reg_reg:
61; CHECK: add r22, r18
62; CHECK: adc r23, r19
63; CHECK: adc r24, r20
64; CHECK: adc r25, r21
65    %result = add i32 %a, %b
66    ret i32 %result
67}
68
69define i32 @add32_reg_imm(i32 %a) {
70; CHECK-LABEL: add32_reg_imm:
71; CHECK: subi r22, 251
72; CHECK: sbci r23, 255
73; CHECK: sbci r24, 255
74; CHECK: sbci r25, 255
75    %result = add i32 %a, 5
76    ret i32 %result
77}
78
79define i32 @add32_reg_reg_zext(i32 %a, i1 zeroext %b) {
80; CHECK-LABEL: add32_reg_reg_zext:
81; CHECK: mov r18, r20
82; CHECK: clr r19
83; CHECK: ldi r20, 0
84; CHECK: ldi r21, 0
85; CHECK: add r22, r18
86; CHECK: adc r23, r19
87; CHECK: adc r24, r20
88; CHECK: adc r25, r21
89    %zext = zext i1 %b to i32
90    %result = add i32 %a, %zext
91    ret i32 %result
92}
93
94define i64 @add64_reg_reg(i64 %a, i64 %b) {
95; CHECK-LABEL: add64_reg_reg:
96; CHECK: add r18, r10
97; CHECK: adc r20, r12
98; CHECK: adc r21, r13
99; CHECK: adc r22, r14
100; CHECK: adc r23, r15
101; CHECK: adc r24, r16
102; CHECK: adc r25, r17
103    %result = add i64 %a, %b
104    ret i64 %result
105}
106
107define i64 @add64_reg_imm(i64 %a) {
108; CHECK-LABEL: add64_reg_imm:
109; CHECK: subi r18, 251
110; CHECK: sbci r19, 255
111; CHECK: sbci r20, 255
112; CHECK: sbci r21, 255
113; CHECK: sbci r22, 255
114; CHECK: sbci r23, 255
115; CHECK: sbci r24, 255
116; CHECK: sbci r25, 255
117    %result = add i64 %a, 5
118    ret i64 %result
119}
120
121define i64 @add64_reg_reg_zext(i64 %a, i1 zeroext %b) {
122; CHECK-LABEL: add64_reg_reg_zext:
123; CHECK: mov r30, r16
124; CHECK: clr r31
125; CHECK: ldi r26, 0
126; CHECK: ldi r27, 0
127; CHECK: add r18, r30
128; CHECK: adc r19, r31
129; CHECK: adc r20, r26
130; CHECK: adc r21, r27
131; CHECK: adc r22, r26
132; CHECK: adc r23, r27
133; CHECK: adc r24, r26
134; CHECK: adc r25, r27
135    %zext = zext i1 %b to i64
136    %result = add i64 %a, %zext
137    ret i64 %result
138}
139