1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s 3 4define <8 x i8> @vmuli8(<8 x i8> %A, <8 x i8> %B) nounwind { 5; CHECK-LABEL: vmuli8: 6; CHECK: @ %bb.0: 7; CHECK-NEXT: vmul.i8 d0, d0, d1 8; CHECK-NEXT: bx lr 9 %tmp3 = mul <8 x i8> %A, %B 10 ret <8 x i8> %tmp3 11} 12 13define <4 x i16> @vmuli16(<4 x i16> %A, <4 x i16> %B) nounwind { 14; CHECK-LABEL: vmuli16: 15; CHECK: @ %bb.0: 16; CHECK-NEXT: vmul.i16 d0, d0, d1 17; CHECK-NEXT: bx lr 18 %tmp3 = mul <4 x i16> %A, %B 19 ret <4 x i16> %tmp3 20} 21 22define <2 x i32> @vmuli32(<2 x i32> %A, <2 x i32> %B) nounwind { 23; CHECK-LABEL: vmuli32: 24; CHECK: @ %bb.0: 25; CHECK-NEXT: vmul.i32 d0, d0, d1 26; CHECK-NEXT: bx lr 27 %tmp3 = mul <2 x i32> %A, %B 28 ret <2 x i32> %tmp3 29} 30 31define <2 x float> @vmulf32(<2 x float> %A, <2 x float> %B) nounwind { 32; CHECK-LABEL: vmulf32: 33; CHECK: @ %bb.0: 34; CHECK-NEXT: vmul.f32 d0, d0, d1 35; CHECK-NEXT: bx lr 36 %tmp3 = fmul <2 x float> %A, %B 37 ret <2 x float> %tmp3 38} 39 40define <8 x i8> @vmulp8(<8 x i8> %A, <8 x i8> %B) nounwind { 41; CHECK-LABEL: vmulp8: 42; CHECK: @ %bb.0: 43; CHECK-NEXT: vmul.p8 d0, d0, d1 44; CHECK-NEXT: bx lr 45 %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %A, <8 x i8> %B) 46 ret <8 x i8> %tmp3 47} 48 49define <16 x i8> @vmulQi8(<16 x i8> %A, <16 x i8> %B) nounwind { 50; CHECK-LABEL: vmulQi8: 51; CHECK: @ %bb.0: 52; CHECK-NEXT: vmul.i8 q0, q0, q1 53; CHECK-NEXT: bx lr 54 %tmp3 = mul <16 x i8> %A, %B 55 ret <16 x i8> %tmp3 56} 57 58define <8 x i16> @vmulQi16(<8 x i16> %A, <8 x i16> %B) nounwind { 59; CHECK-LABEL: vmulQi16: 60; CHECK: @ %bb.0: 61; CHECK-NEXT: vmul.i16 q0, q0, q1 62; CHECK-NEXT: bx lr 63 %tmp3 = mul <8 x i16> %A, %B 64 ret <8 x i16> %tmp3 65} 66 67define <4 x i32> @vmulQi32(<4 x i32> %A, <4 x i32> %B) nounwind { 68; CHECK-LABEL: vmulQi32: 69; CHECK: @ %bb.0: 70; CHECK-NEXT: vmul.i32 q0, q0, q1 71; CHECK-NEXT: bx lr 72 %tmp3 = mul <4 x i32> %A, %B 73 ret <4 x i32> %tmp3 74} 75 76define <4 x float> @vmulQf32(<4 x float> %A, <4 x float> %B) nounwind { 77; CHECK-LABEL: vmulQf32: 78; CHECK: @ %bb.0: 79; CHECK-NEXT: vmul.f32 q0, q0, q1 80; CHECK-NEXT: bx lr 81 %tmp3 = fmul <4 x float> %A, %B 82 ret <4 x float> %tmp3 83} 84 85define <16 x i8> @vmulQp8(<16 x i8> %A, <16 x i8> %B) nounwind { 86; CHECK-LABEL: vmulQp8: 87; CHECK: @ %bb.0: 88; CHECK-NEXT: vmul.p8 q0, q0, q1 89; CHECK-NEXT: bx lr 90 %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %A, <16 x i8> %B) 91 ret <16 x i8> %tmp3 92} 93 94declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 95declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone 96 97define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone { 98; CHECK-LABEL: test_vmul_lanef32: 99; CHECK: @ %bb.0: @ %entry 100; CHECK-NEXT: vmul.f32 d0, d0, d1[0] 101; CHECK-NEXT: bx lr 102entry: 103 %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1] 104 %1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1] 105 ret <2 x float> %1 106} 107 108define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone { 109; CHECK-LABEL: test_vmul_lanes16: 110; CHECK: @ %bb.0: @ %entry 111; CHECK-NEXT: vmul.i16 d0, d0, d1[1] 112; CHECK-NEXT: bx lr 113entry: 114 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$ 115 %1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1] 116 ret <4 x i16> %1 117} 118 119define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { 120; CHECK-LABEL: test_vmul_lanes32: 121; CHECK: @ %bb.0: @ %entry 122; CHECK-NEXT: vmul.i32 d0, d0, d1[1] 123; CHECK-NEXT: bx lr 124entry: 125 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] 126 %1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1] 127 ret <2 x i32> %1 128} 129 130define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone { 131; CHECK-LABEL: test_vmulQ_lanef32: 132; CHECK: @ %bb.0: @ %entry 133; CHECK-NEXT: @ kill: def $d2 killed $d2 def $q1 134; CHECK-NEXT: vmul.f32 q0, q0, d2[1] 135; CHECK-NEXT: bx lr 136entry: 137 %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$ 138 %1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1] 139 ret <4 x float> %1 140} 141 142define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone { 143; CHECK-LABEL: test_vmulQ_lanes16: 144; CHECK: @ %bb.0: @ %entry 145; CHECK-NEXT: @ kill: def $d2 killed $d2 def $q1 146; CHECK-NEXT: vmul.i16 q0, q0, d2[1] 147; CHECK-NEXT: bx lr 148entry: 149 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 150 %1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1] 151 ret <8 x i16> %1 152} 153 154define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { 155; CHECK-LABEL: test_vmulQ_lanes32: 156; CHECK: @ %bb.0: @ %entry 157; CHECK-NEXT: @ kill: def $d2 killed $d2 def $q1 158; CHECK-NEXT: vmul.i32 q0, q0, d2[1] 159; CHECK-NEXT: bx lr 160entry: 161 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$ 162 %1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1] 163 ret <4 x i32> %1 164} 165 166define <8 x i16> @vmulls8(<8 x i8> %A, <8 x i8> %B) nounwind { 167; CHECK-LABEL: vmulls8: 168; CHECK: @ %bb.0: 169; CHECK-NEXT: vmull.s8 q0, d0, d1 170; CHECK-NEXT: bx lr 171 %tmp3 = sext <8 x i8> %A to <8 x i16> 172 %tmp4 = sext <8 x i8> %B to <8 x i16> 173 %tmp5 = mul <8 x i16> %tmp3, %tmp4 174 ret <8 x i16> %tmp5 175} 176 177define <8 x i16> @vmulls8_int(<8 x i8> %A, <8 x i8> %B) nounwind { 178; CHECK-LABEL: vmulls8_int: 179; CHECK: @ %bb.0: 180; CHECK-NEXT: vmull.s8 q0, d0, d1 181; CHECK-NEXT: bx lr 182 %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %A, <8 x i8> %B) 183 ret <8 x i16> %tmp3 184} 185 186define <4 x i32> @vmulls16(<4 x i16> %A, <4 x i16> %B) nounwind { 187; CHECK-LABEL: vmulls16: 188; CHECK: @ %bb.0: 189; CHECK-NEXT: vmull.s16 q0, d0, d1 190; CHECK-NEXT: bx lr 191 %tmp3 = sext <4 x i16> %A to <4 x i32> 192 %tmp4 = sext <4 x i16> %B to <4 x i32> 193 %tmp5 = mul <4 x i32> %tmp3, %tmp4 194 ret <4 x i32> %tmp5 195} 196 197define <4 x i32> @vmulls16_int(<4 x i16> %A, <4 x i16> %B) nounwind { 198; CHECK-LABEL: vmulls16_int: 199; CHECK: @ %bb.0: 200; CHECK-NEXT: vmull.s16 q0, d0, d1 201; CHECK-NEXT: bx lr 202 %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %A, <4 x i16> %B) 203 ret <4 x i32> %tmp3 204} 205 206define <2 x i64> @vmulls32(<2 x i32> %A, <2 x i32> %B) nounwind { 207; CHECK-LABEL: vmulls32: 208; CHECK: @ %bb.0: 209; CHECK-NEXT: vmull.s32 q0, d0, d1 210; CHECK-NEXT: bx lr 211 %tmp3 = sext <2 x i32> %A to <2 x i64> 212 %tmp4 = sext <2 x i32> %B to <2 x i64> 213 %tmp5 = mul <2 x i64> %tmp3, %tmp4 214 ret <2 x i64> %tmp5 215} 216 217define <2 x i64> @vmulls32_int(<2 x i32> %A, <2 x i32> %B) nounwind { 218; CHECK-LABEL: vmulls32_int: 219; CHECK: @ %bb.0: 220; CHECK-NEXT: vmull.s32 q0, d0, d1 221; CHECK-NEXT: bx lr 222 %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %A, <2 x i32> %B) 223 ret <2 x i64> %tmp3 224} 225 226define <8 x i16> @vmullu8(<8 x i8> %A, <8 x i8> %B) nounwind { 227; CHECK-LABEL: vmullu8: 228; CHECK: @ %bb.0: 229; CHECK-NEXT: vmull.u8 q0, d0, d1 230; CHECK-NEXT: bx lr 231 %tmp3 = zext <8 x i8> %A to <8 x i16> 232 %tmp4 = zext <8 x i8> %B to <8 x i16> 233 %tmp5 = mul <8 x i16> %tmp3, %tmp4 234 ret <8 x i16> %tmp5 235} 236 237define <8 x i16> @vmullu8_int(<8 x i8> %A, <8 x i8> %B) nounwind { 238; CHECK-LABEL: vmullu8_int: 239; CHECK: @ %bb.0: 240; CHECK-NEXT: vmull.u8 q0, d0, d1 241; CHECK-NEXT: bx lr 242 %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %A, <8 x i8> %B) 243 ret <8 x i16> %tmp3 244} 245 246define <4 x i32> @vmullu16(<4 x i16> %A, <4 x i16> %B) nounwind { 247; CHECK-LABEL: vmullu16: 248; CHECK: @ %bb.0: 249; CHECK-NEXT: vmull.u16 q0, d0, d1 250; CHECK-NEXT: bx lr 251 %tmp3 = zext <4 x i16> %A to <4 x i32> 252 %tmp4 = zext <4 x i16> %B to <4 x i32> 253 %tmp5 = mul <4 x i32> %tmp3, %tmp4 254 ret <4 x i32> %tmp5 255} 256 257define <4 x i32> @vmullu16_int(<4 x i16> %A, <4 x i16> %B) nounwind { 258; CHECK-LABEL: vmullu16_int: 259; CHECK: @ %bb.0: 260; CHECK-NEXT: vmull.u16 q0, d0, d1 261; CHECK-NEXT: bx lr 262 %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %A, <4 x i16> %B) 263 ret <4 x i32> %tmp3 264} 265 266define <2 x i64> @vmullu32(<2 x i32> %A, <2 x i32> %B) nounwind { 267; CHECK-LABEL: vmullu32: 268; CHECK: @ %bb.0: 269; CHECK-NEXT: vmull.u32 q0, d0, d1 270; CHECK-NEXT: bx lr 271 %tmp3 = zext <2 x i32> %A to <2 x i64> 272 %tmp4 = zext <2 x i32> %B to <2 x i64> 273 %tmp5 = mul <2 x i64> %tmp3, %tmp4 274 ret <2 x i64> %tmp5 275} 276 277define <2 x i64> @vmullu32_int(<2 x i32> %A, <2 x i32> %B) nounwind { 278; CHECK-LABEL: vmullu32_int: 279; CHECK: @ %bb.0: 280; CHECK-NEXT: vmull.u32 q0, d0, d1 281; CHECK-NEXT: bx lr 282 %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %A, <2 x i32> %B) 283 ret <2 x i64> %tmp3 284} 285 286define <8 x i16> @vmulla8(<8 x i8> %A, <8 x i8> %B) nounwind { 287; CHECK-LABEL: vmulla8: 288; CHECK: @ %bb.0: 289; CHECK-NEXT: vmull.u8 q0, d0, d1 290; CHECK-NEXT: vbic.i16 q0, #0xff00 291; CHECK-NEXT: bx lr 292 %tmp3 = zext <8 x i8> %A to <8 x i16> 293 %tmp4 = zext <8 x i8> %B to <8 x i16> 294 %tmp5 = mul <8 x i16> %tmp3, %tmp4 295 %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 296 ret <8 x i16> %and 297} 298 299define <4 x i32> @vmulla16(<4 x i16> %A, <4 x i16> %B) nounwind { 300; CHECK-LABEL: vmulla16: 301; CHECK: @ %bb.0: 302; CHECK-NEXT: vmull.u16 q8, d0, d1 303; CHECK-NEXT: vmov.i32 q9, #0xffff 304; CHECK-NEXT: vand q0, q8, q9 305; CHECK-NEXT: bx lr 306 %tmp3 = zext <4 x i16> %A to <4 x i32> 307 %tmp4 = zext <4 x i16> %B to <4 x i32> 308 %tmp5 = mul <4 x i32> %tmp3, %tmp4 309 %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535> 310 ret <4 x i32> %and 311} 312 313define <2 x i64> @vmulla32(<2 x i32> %A, <2 x i32> %B) nounwind { 314; CHECK-LABEL: vmulla32: 315; CHECK: @ %bb.0: 316; CHECK-NEXT: vmull.u32 q8, d0, d1 317; CHECK-NEXT: vmov.i64 q9, #0xffffffff 318; CHECK-NEXT: vand q0, q8, q9 319; CHECK-NEXT: bx lr 320 %tmp3 = zext <2 x i32> %A to <2 x i64> 321 %tmp4 = zext <2 x i32> %B to <2 x i64> 322 %tmp5 = mul <2 x i64> %tmp3, %tmp4 323 %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295> 324 ret <2 x i64> %and 325} 326 327define <8 x i16> @vmullp8(<8 x i8> %A, <8 x i8> %B) nounwind { 328; CHECK-LABEL: vmullp8: 329; CHECK: @ %bb.0: 330; CHECK-NEXT: vmull.p8 q0, d0, d1 331; CHECK-NEXT: bx lr 332 %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %A, <8 x i8> %B) 333 ret <8 x i16> %tmp3 334} 335 336define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone { 337; CHECK-LABEL: test_vmull_lanes16: 338; CHECK: @ %bb.0: @ %entry 339; CHECK-NEXT: vmull.s16 q0, d0, d1[1] 340; CHECK-NEXT: bx lr 341entry: 342 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] 343 %1 = sext <4 x i16> %arg0_int16x4_t to <4 x i32> 344 %2 = sext <4 x i16> %0 to <4 x i32> 345 %3 = mul <4 x i32> %1, %2 346 ret <4 x i32> %3 347} 348 349define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16_int(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone { 350; CHECK-LABEL: test_vmull_lanes16_int: 351; CHECK: @ %bb.0: @ %entry 352; CHECK-NEXT: vmull.s16 q0, d0, d1[1] 353; CHECK-NEXT: bx lr 354entry: 355 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] 356 %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] 357 ret <4 x i32> %1 358} 359 360define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { 361; CHECK-LABEL: test_vmull_lanes32: 362; CHECK: @ %bb.0: @ %entry 363; CHECK-NEXT: vmull.s32 q0, d0, d1[1] 364; CHECK-NEXT: bx lr 365entry: 366 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] 367 %1 = sext <2 x i32> %arg0_int32x2_t to <2 x i64> 368 %2 = sext <2 x i32> %0 to <2 x i64> 369 %3 = mul <2 x i64> %1, %2 370 ret <2 x i64> %3 371} 372 373define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32_int(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { 374; CHECK-LABEL: test_vmull_lanes32_int: 375; CHECK: @ %bb.0: @ %entry 376; CHECK-NEXT: vmull.s32 q0, d0, d1[1] 377; CHECK-NEXT: bx lr 378entry: 379 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] 380 %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] 381 ret <2 x i64> %1 382} 383 384define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone { 385; CHECK-LABEL: test_vmull_laneu16: 386; CHECK: @ %bb.0: @ %entry 387; CHECK-NEXT: vmull.u16 q0, d0, d1[1] 388; CHECK-NEXT: bx lr 389entry: 390 %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] 391 %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32> 392 %2 = zext <4 x i16> %0 to <4 x i32> 393 %3 = mul <4 x i32> %1, %2 394 ret <4 x i32> %3 395} 396 397define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16_int(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone { 398; CHECK-LABEL: test_vmull_laneu16_int: 399; CHECK: @ %bb.0: @ %entry 400; CHECK-NEXT: vmull.u16 q0, d0, d1[1] 401; CHECK-NEXT: bx lr 402entry: 403 %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] 404 %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] 405 ret <4 x i32> %1 406} 407 408define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone { 409; CHECK-LABEL: test_vmull_laneu32: 410; CHECK: @ %bb.0: @ %entry 411; CHECK-NEXT: vmull.u32 q0, d0, d1[1] 412; CHECK-NEXT: bx lr 413entry: 414 %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] 415 %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64> 416 %2 = zext <2 x i32> %0 to <2 x i64> 417 %3 = mul <2 x i64> %1, %2 418 ret <2 x i64> %3 419} 420 421define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32_int(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone { 422; CHECK-LABEL: test_vmull_laneu32_int: 423; CHECK: @ %bb.0: @ %entry 424; CHECK-NEXT: vmull.u32 q0, d0, d1[1] 425; CHECK-NEXT: bx lr 426entry: 427 %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] 428 %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] 429 ret <2 x i64> %1 430} 431 432define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanea16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone { 433; CHECK-LABEL: test_vmull_lanea16: 434; CHECK: @ %bb.0: @ %entry 435; CHECK-NEXT: vmull.u16 q8, d0, d1[1] 436; CHECK-NEXT: vmov.i32 q9, #0xffff 437; CHECK-NEXT: vand q0, q8, q9 438; CHECK-NEXT: bx lr 439entry: 440 %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] 441 %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32> 442 %2 = zext <4 x i16> %0 to <4 x i32> 443 %3 = mul <4 x i32> %1, %2 444 %and = and <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535> 445 ret <4 x i32> %and 446} 447 448define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanea32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone { 449; CHECK-LABEL: test_vmull_lanea32: 450; CHECK: @ %bb.0: @ %entry 451; CHECK-NEXT: vmull.u32 q8, d0, d1[1] 452; CHECK-NEXT: vmov.i64 q9, #0xffffffff 453; CHECK-NEXT: vand q0, q8, q9 454; CHECK-NEXT: bx lr 455entry: 456 %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] 457 %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64> 458 %2 = zext <2 x i32> %0 to <2 x i64> 459 %3 = mul <2 x i64> %1, %2 460 %and = and <2 x i64> %3, <i64 4294967295, i64 4294967295> 461 ret <2 x i64> %and 462} 463 464declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone 465declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone 466declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone 467 468declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone 469declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone 470declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone 471 472declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone 473 474 475; Radar 8687140 476; VMULL needs to recognize BUILD_VECTORs with sign/zero-extended elements. 477 478define <8 x i16> @vmull_extvec_s8(<8 x i8> %arg) nounwind { 479; CHECK-LABEL: vmull_extvec_s8: 480; CHECK: @ %bb.0: 481; CHECK-NEXT: vmov.i8 d16, #0xf4 482; CHECK-NEXT: vmull.s8 q0, d0, d16 483; CHECK-NEXT: bx lr 484 %tmp3 = sext <8 x i8> %arg to <8 x i16> 485 %tmp4 = mul <8 x i16> %tmp3, <i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12> 486 ret <8 x i16> %tmp4 487} 488 489define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind { 490; CHECK-LABEL: vmull_extvec_u8: 491; CHECK: @ %bb.0: 492; CHECK-NEXT: vmov.i8 d16, #0xc 493; CHECK-NEXT: vmull.u8 q0, d0, d16 494; CHECK-NEXT: bx lr 495 %tmp3 = zext <8 x i8> %arg to <8 x i16> 496 %tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12> 497 ret <8 x i16> %tmp4 498} 499 500define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind { 501; Do not use VMULL if the BUILD_VECTOR element values are too big. 502; CHECK-LABEL: vmull_noextvec_s8: 503; CHECK: @ %bb.0: 504; CHECK-NEXT: vmovl.s8 q8, d0 505; CHECK-NEXT: adr r0, .LCPI44_0 506; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128] 507; CHECK-NEXT: vmul.i16 q0, q8, q9 508; CHECK-NEXT: bx lr 509; CHECK-NEXT: .p2align 4 510; CHECK-NEXT: @ %bb.1: 511; CHECK-NEXT: .LCPI44_0: 512; CHECK-NEXT: .short 64537 @ 0xfc19 513; CHECK-NEXT: .short 64537 @ 0xfc19 514; CHECK-NEXT: .short 64537 @ 0xfc19 515; CHECK-NEXT: .short 64537 @ 0xfc19 516; CHECK-NEXT: .short 64537 @ 0xfc19 517; CHECK-NEXT: .short 64537 @ 0xfc19 518; CHECK-NEXT: .short 64537 @ 0xfc19 519; CHECK-NEXT: .short 64537 @ 0xfc19 520 %tmp3 = sext <8 x i8> %arg to <8 x i16> 521 %tmp4 = mul <8 x i16> %tmp3, <i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999> 522 ret <8 x i16> %tmp4 523} 524 525define <8 x i16> @vmull_noextvec_u8(<8 x i8> %arg) nounwind { 526; Do not use VMULL if the BUILD_VECTOR element values are too big. 527; CHECK-LABEL: vmull_noextvec_u8: 528; CHECK: @ %bb.0: 529; CHECK-NEXT: vmovl.u8 q8, d0 530; CHECK-NEXT: adr r0, .LCPI45_0 531; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128] 532; CHECK-NEXT: vmul.i16 q0, q8, q9 533; CHECK-NEXT: bx lr 534; CHECK-NEXT: .p2align 4 535; CHECK-NEXT: @ %bb.1: 536; CHECK-NEXT: .LCPI45_0: 537; CHECK-NEXT: .short 999 @ 0x3e7 538; CHECK-NEXT: .short 999 @ 0x3e7 539; CHECK-NEXT: .short 999 @ 0x3e7 540; CHECK-NEXT: .short 999 @ 0x3e7 541; CHECK-NEXT: .short 999 @ 0x3e7 542; CHECK-NEXT: .short 999 @ 0x3e7 543; CHECK-NEXT: .short 999 @ 0x3e7 544; CHECK-NEXT: .short 999 @ 0x3e7 545 %tmp3 = zext <8 x i8> %arg to <8 x i16> 546 %tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999> 547 ret <8 x i16> %tmp4 548} 549 550define <4 x i32> @vmull_extvec_s16(<4 x i16> %arg) nounwind { 551; CHECK-LABEL: vmull_extvec_s16: 552; CHECK: @ %bb.0: 553; CHECK-NEXT: vmvn.i16 d16, #0xb 554; CHECK-NEXT: vmull.s16 q0, d0, d16 555; CHECK-NEXT: bx lr 556 %tmp3 = sext <4 x i16> %arg to <4 x i32> 557 %tmp4 = mul <4 x i32> %tmp3, <i32 -12, i32 -12, i32 -12, i32 -12> 558 ret <4 x i32> %tmp4 559} 560 561define <4 x i32> @vmull_extvec_u16(<4 x i16> %arg) nounwind { 562; CHECK-LABEL: vmull_extvec_u16: 563; CHECK: @ %bb.0: 564; CHECK-NEXT: vldr d16, .LCPI47_0 565; CHECK-NEXT: vmull.u16 q0, d0, d16 566; CHECK-NEXT: bx lr 567; CHECK-NEXT: .p2align 3 568; CHECK-NEXT: @ %bb.1: 569; CHECK-NEXT: .LCPI47_0: 570; CHECK-NEXT: .short 1234 @ 0x4d2 571; CHECK-NEXT: .short 1234 @ 0x4d2 572; CHECK-NEXT: .short 1234 @ 0x4d2 573; CHECK-NEXT: .short 1234 @ 0x4d2 574 %tmp3 = zext <4 x i16> %arg to <4 x i32> 575 %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234> 576 ret <4 x i32> %tmp4 577} 578 579define <2 x i64> @vmull_extvec_s32(<2 x i32> %arg) nounwind { 580; CHECK-LABEL: vmull_extvec_s32: 581; CHECK: @ %bb.0: 582; CHECK-NEXT: vldr d16, .LCPI48_0 583; CHECK-NEXT: vmull.s32 q0, d0, d16 584; CHECK-NEXT: bx lr 585; CHECK-NEXT: .p2align 3 586; CHECK-NEXT: @ %bb.1: 587; CHECK-NEXT: .LCPI48_0: 588; CHECK-NEXT: .long 4294966062 @ 0xfffffb2e 589; CHECK-NEXT: .long 4294966062 @ 0xfffffb2e 590 %tmp3 = sext <2 x i32> %arg to <2 x i64> 591 %tmp4 = mul <2 x i64> %tmp3, <i64 -1234, i64 -1234> 592 ret <2 x i64> %tmp4 593} 594 595define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind { 596; CHECK-LABEL: vmull_extvec_u32: 597; CHECK: @ %bb.0: 598; CHECK-NEXT: vldr d16, .LCPI49_0 599; CHECK-NEXT: vmull.u32 q0, d0, d16 600; CHECK-NEXT: bx lr 601; CHECK-NEXT: .p2align 3 602; CHECK-NEXT: @ %bb.1: 603; CHECK-NEXT: .LCPI49_0: 604; CHECK-NEXT: .long 1234 @ 0x4d2 605; CHECK-NEXT: .long 1234 @ 0x4d2 606 %tmp3 = zext <2 x i32> %arg to <2 x i64> 607 %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234> 608 ret <2 x i64> %tmp4 609} 610 611; rdar://9197392 612define void @distribute(ptr %dst, ptr %src, i32 %mul) nounwind { 613; CHECK-LABEL: distribute: 614; CHECK: @ %bb.0: @ %entry 615; CHECK-NEXT: vld1.8 {d16, d17}, [r1] 616; CHECK-NEXT: vdup.8 d18, r2 617; CHECK-NEXT: vmull.u8 q10, d17, d18 618; CHECK-NEXT: vmlal.u8 q10, d16, d18 619; CHECK-NEXT: vst1.16 {d20, d21}, [r0] 620; CHECK-NEXT: bx lr 621entry: 622 %0 = trunc i32 %mul to i8 623 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 624 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer 625 %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1) 626 %4 = bitcast <16 x i8> %3 to <2 x double> 627 %5 = extractelement <2 x double> %4, i32 1 628 %6 = bitcast double %5 to <8 x i8> 629 %7 = zext <8 x i8> %6 to <8 x i16> 630 %8 = zext <8 x i8> %2 to <8 x i16> 631 %9 = extractelement <2 x double> %4, i32 0 632 %10 = bitcast double %9 to <8 x i8> 633 %11 = zext <8 x i8> %10 to <8 x i16> 634 %12 = add <8 x i16> %7, %11 635 %13 = mul <8 x i16> %12, %8 636 tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %dst, <8 x i16> %13, i32 2) 637 ret void 638} 639 640declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr, i32) nounwind readonly 641 642declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind 643 644; Take advantage of the Cortex-A8 multiplier accumulator forward. 645 646%struct.uint8x8_t = type { <8 x i8> } 647 648define void @distribute2(ptr nocapture %dst, ptr %src, i32 %mul) nounwind { 649; CHECK-LABEL: distribute2: 650; CHECK: @ %bb.0: @ %entry 651; CHECK-NEXT: vld1.8 {d16, d17}, [r1] 652; CHECK-NEXT: vadd.i8 d16, d17, d16 653; CHECK-NEXT: vdup.8 d17, r2 654; CHECK-NEXT: vmul.i8 d16, d16, d17 655; CHECK-NEXT: vstr d16, [r0] 656; CHECK-NEXT: bx lr 657entry: 658 %0 = trunc i32 %mul to i8 659 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 660 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer 661 %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1) 662 %4 = bitcast <16 x i8> %3 to <2 x double> 663 %5 = extractelement <2 x double> %4, i32 1 664 %6 = bitcast double %5 to <8 x i8> 665 %7 = extractelement <2 x double> %4, i32 0 666 %8 = bitcast double %7 to <8 x i8> 667 %9 = add <8 x i8> %6, %8 668 %10 = mul <8 x i8> %9, %2 669 store <8 x i8> %10, ptr %dst, align 8 670 ret void 671} 672 673define void @distribute2_commutative(ptr nocapture %dst, ptr %src, i32 %mul) nounwind { 674; CHECK-LABEL: distribute2_commutative: 675; CHECK: @ %bb.0: @ %entry 676; CHECK-NEXT: vld1.8 {d16, d17}, [r1] 677; CHECK-NEXT: vadd.i8 d16, d17, d16 678; CHECK-NEXT: vdup.8 d17, r2 679; CHECK-NEXT: vmul.i8 d16, d17, d16 680; CHECK-NEXT: vstr d16, [r0] 681; CHECK-NEXT: bx lr 682entry: 683 %0 = trunc i32 %mul to i8 684 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 685 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer 686 %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1) 687 %4 = bitcast <16 x i8> %3 to <2 x double> 688 %5 = extractelement <2 x double> %4, i32 1 689 %6 = bitcast double %5 to <8 x i8> 690 %7 = extractelement <2 x double> %4, i32 0 691 %8 = bitcast double %7 to <8 x i8> 692 %9 = add <8 x i8> %6, %8 693 %10 = mul <8 x i8> %2, %9 694 store <8 x i8> %10, ptr %dst, align 8 695 ret void 696} 697 698define <8 x i8> @no_distribute(<8 x i8> %a, <8 x i8> %b) nounwind { 699; CHECK-LABEL: no_distribute: 700; CHECK: @ %bb.0: @ %entry 701; CHECK-NEXT: vadd.i8 d16, d0, d1 702; CHECK-NEXT: vmul.i8 d0, d16, d16 703; CHECK-NEXT: bx lr 704entry: 705 %0 = add <8 x i8> %a, %b 706 %1 = mul <8x i8> %0, %0 707 ret <8 x i8> %1 708} 709 710; If one operand has a zero-extend and the other a sign-extend, vmull 711; cannot be used. 712define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) { 713; CHECK-LABEL: vmullWithInconsistentExtensions: 714; CHECK: @ %bb.0: 715; CHECK-NEXT: vmovl.s8 q8, d0 716; CHECK-NEXT: vmov.i16 q9, #0xff 717; CHECK-NEXT: vmul.i16 q8, q8, q9 718; CHECK-NEXT: vmov.u16 r0, d16[0] 719; CHECK-NEXT: bx lr 720 %1 = sext <8 x i8> %vec to <8 x i16> 721 %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 722 %3 = extractelement <8 x i16> %2, i32 0 723 ret i16 %3 724} 725 726; A constant build_vector created for a vmull with half-width elements must 727; not introduce illegal types. <rdar://problem/11324364> 728define void @vmull_buildvector() nounwind optsize ssp align 2 { 729; CHECK-LABEL: vmull_buildvector: 730; CHECK: @ %bb.0: @ %entry 731entry: 732 br i1 undef, label %for.end179, label %for.body.lr.ph 733 734for.body.lr.ph: ; preds = %entry 735 br label %for.body 736 737for.cond.loopexit: ; preds = %for.body33, %for.body 738 br i1 undef, label %for.end179, label %for.body 739 740for.body: ; preds = %for.cond.loopexit, %for.body.lr.ph 741 br i1 undef, label %for.cond.loopexit, label %for.body33.lr.ph 742 743for.body33.lr.ph: ; preds = %for.body 744 %.sub = select i1 undef, i32 0, i32 undef 745 br label %for.body33 746 747for.body33: ; preds = %for.body33, %for.body33.lr.ph 748 %add45 = add i32 undef, undef 749 %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr undef, i32 1) 750 %0 = load ptr, ptr undef, align 4 751 %shuffle.i250 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer 752 %1 = bitcast <1 x i64> %shuffle.i250 to <8 x i8> 753 %vmovl.i249 = zext <8 x i8> %1 to <8 x i16> 754 %shuffle.i246 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer 755 %shuffle.i240 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> <i32 1> 756 %2 = bitcast <1 x i64> %shuffle.i240 to <8 x i8> 757 %3 = bitcast <16 x i8> undef to <2 x i64> 758 %vmovl.i237 = zext <8 x i8> undef to <8 x i16> 759 %shuffle.i234 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer 760 %shuffle.i226 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer 761 %vmovl.i225 = zext <8 x i8> undef to <8 x i16> 762 %mul.i223 = mul <8 x i16> %vmovl.i249, %vmovl.i249 763 %vshl_n = shl <8 x i16> %mul.i223, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 764 %vqsub2.i216 = tail call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>, <8 x i16> %vshl_n) nounwind 765 %mul.i209 = mul <8 x i16> undef, <i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80> 766 %vshr_n130 = lshr <8 x i16> undef, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> 767 %vshr_n134 = lshr <8 x i16> %mul.i209, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> 768 %sub.i205 = sub <8 x i16> <i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80>, %vshr_n130 769 %sub.i203 = sub <8 x i16> <i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80>, %vshr_n134 770 %add.i200 = add <8 x i16> %sub.i205, <i16 96, i16 96, i16 96, i16 96, i16 96, i16 96, i16 96, i16 96> 771 %add.i198 = add <8 x i16> %add.i200, %sub.i203 772 %mul.i194 = mul <8 x i16> %add.i198, %vmovl.i237 773 %mul.i191 = mul <8 x i16> %vshr_n130, undef 774 %add.i192 = add <8 x i16> %mul.i191, %mul.i194 775 %mul.i187 = mul <8 x i16> %vshr_n134, undef 776 %add.i188 = add <8 x i16> %mul.i187, %add.i192 777 %mul.i185 = mul <8 x i16> undef, undef 778 %add.i186 = add <8 x i16> %mul.i185, undef 779 %vrshr_n160 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i188, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>) 780 %vrshr_n163 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i186, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>) 781 %mul.i184 = mul <8 x i16> undef, %vrshr_n160 782 %mul.i181 = mul <8 x i16> undef, %vmovl.i225 783 %add.i182 = add <8 x i16> %mul.i181, %mul.i184 784 %vrshr_n170 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i182, <8 x i16> <i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7>) 785 %vqmovn1.i180 = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %vrshr_n170) nounwind 786 %4 = bitcast <8 x i8> %vqmovn1.i180 to <1 x i64> 787 %shuffle.i = shufflevector <1 x i64> %4, <1 x i64> undef, <2 x i32> <i32 0, i32 1> 788 %5 = bitcast <2 x i64> %shuffle.i to <16 x i8> 789 store <16 x i8> %5, ptr undef, align 16 790 %add177 = add nsw i32 undef, 16 791 br i1 undef, label %for.body33, label %for.cond.loopexit 792 793for.end179: ; preds = %for.cond.loopexit, %entry 794 ret void 795} 796 797declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone 798declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone 799declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone 800 801; vmull lowering would create a zext(v4i8 load()) instead of a zextload(v4i8), 802; creating an illegal type during legalization and causing an assert. 803; PR15970 804define void @no_illegal_types_vmull_sext(<4 x i32> %a) { 805; CHECK-LABEL: no_illegal_types_vmull_sext: 806; CHECK: @ %bb.0: @ %entry 807entry: 808 %wide.load283.i = load <4 x i8>, ptr undef, align 1 809 %0 = sext <4 x i8> %wide.load283.i to <4 x i32> 810 %1 = sub nsw <4 x i32> %0, %a 811 %2 = mul nsw <4 x i32> %1, %1 812 %predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2 813 store <4 x i32> %predphi290.v.i, ptr undef, align 4 814 ret void 815} 816define void @no_illegal_types_vmull_zext(<4 x i32> %a) { 817; CHECK-LABEL: no_illegal_types_vmull_zext: 818; CHECK: @ %bb.0: @ %entry 819entry: 820 %wide.load283.i = load <4 x i8>, ptr undef, align 1 821 %0 = zext <4 x i8> %wide.load283.i to <4 x i32> 822 %1 = sub nsw <4 x i32> %0, %a 823 %2 = mul nsw <4 x i32> %1, %1 824 %predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2 825 store <4 x i32> %predphi290.v.i, ptr undef, align 4 826 ret void 827} 828 829define void @fmul_splat(ptr %A, ptr nocapture %dst, float %tmp) nounwind { 830; Look for a scalar float rather than a splat, then a vector*scalar multiply. 831; CHECK-LABEL: fmul_splat: 832; CHECK: @ %bb.0: 833; CHECK-NEXT: vld1.32 {d16, d17}, [r0] 834; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d0 835; CHECK-NEXT: vmul.f32 q8, q8, d0[0] 836; CHECK-NEXT: vst1.32 {d16, d17}, [r1] 837; CHECK-NEXT: bx lr 838 %tmp5 = load <4 x float>, ptr %A, align 4 839 %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0 840 %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1 841 %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2 842 %tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3 843 %tmp10 = fmul <4 x float> %tmp9, %tmp5 844 store <4 x float> %tmp10, ptr %dst, align 4 845 ret void 846} 847 848define void @fmul_splat_load(ptr %A, ptr nocapture %dst, ptr nocapture readonly %src) nounwind { 849; Look for doing a normal scalar FP load rather than an to-all-lanes load, 850; then a vector*scalar multiply. 851; FIXME: Temporarily broken due to splat representation changes. 852; CHECK-LABEL: fmul_splat_load: 853; CHECK: @ %bb.0: 854; CHECK-NEXT: vld1.32 {d16, d17}, [r0] 855; CHECK-NEXT: vld1.32 {d18[], d19[]}, [r2:32] 856; CHECK-NEXT: vmul.f32 q8, q9, q8 857; CHECK-NEXT: vst1.32 {d16, d17}, [r1] 858; CHECK-NEXT: bx lr 859 %tmp = load float, ptr %src, align 4 860 %tmp5 = load <4 x float>, ptr %A, align 4 861 %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0 862 %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1 863 %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2 864 %tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3 865 %tmp10 = fmul <4 x float> %tmp9, %tmp5 866 store <4 x float> %tmp10, ptr %dst, align 4 867 ret void 868} 869