1; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s 2 3; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \ 4; RUN: | FileCheck %s 5 6define <8 x i8> @vld1i8(ptr %A) nounwind { 7;CHECK-LABEL: vld1i8: 8;Check the alignment value. Max for this instruction is 64 bits: 9;CHECK: vld1.8 {d16}, [r0:64] 10 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %A, i32 16) 11 ret <8 x i8> %tmp1 12} 13 14define <4 x i16> @vld1i16(ptr %A) nounwind { 15;CHECK-LABEL: vld1i16: 16;CHECK: vld1.16 17 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr %A, i32 1) 18 ret <4 x i16> %tmp1 19} 20 21;Check for a post-increment updating load. 22define <4 x i16> @vld1i16_update(ptr %ptr) nounwind { 23;CHECK-LABEL: vld1i16_update: 24;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]! 25 %A = load ptr, ptr %ptr 26 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr %A, i32 1) 27 %tmp2 = getelementptr i16, ptr %A, i32 4 28 store ptr %tmp2, ptr %ptr 29 ret <4 x i16> %tmp1 30} 31 32define <2 x i32> @vld1i32(ptr %A) nounwind { 33;CHECK-LABEL: vld1i32: 34;CHECK: vld1.32 35 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr %A, i32 1) 36 ret <2 x i32> %tmp1 37} 38 39;Check for a post-increment updating load with register increment. 40define <2 x i32> @vld1i32_update(ptr %ptr, i32 %inc) nounwind { 41;CHECK-LABEL: vld1i32_update: 42;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}} 43 %A = load ptr, ptr %ptr 44 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr %A, i32 1) 45 %tmp2 = getelementptr i32, ptr %A, i32 %inc 46 store ptr %tmp2, ptr %ptr 47 ret <2 x i32> %tmp1 48} 49 50define <2 x float> @vld1f(ptr %A) nounwind { 51;CHECK-LABEL: vld1f: 52;CHECK: vld1.32 53 %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr %A, i32 1) 54 ret <2 x float> %tmp1 55} 56 57define <1 x i64> @vld1i64(ptr %A) nounwind { 58;CHECK-LABEL: vld1i64: 59;CHECK: vld1.64 60 %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %A, i32 1) 61 ret <1 x i64> %tmp1 62} 63 64define <16 x i8> @vld1Qi8(ptr %A) nounwind { 65;CHECK-LABEL: vld1Qi8: 66;Check the alignment value. Max for this instruction is 128 bits: 67;CHECK: vld1.8 {d16, d17}, [r0:64] 68 %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %A, i32 8) 69 ret <16 x i8> %tmp1 70} 71 72;Check for a post-increment updating load. 73define <16 x i8> @vld1Qi8_update(ptr %ptr) nounwind { 74;CHECK-LABEL: vld1Qi8_update: 75;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+|lr}}:64]! 76 %A = load ptr, ptr %ptr 77 %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %A, i32 8) 78 %tmp2 = getelementptr i8, ptr %A, i32 16 79 store ptr %tmp2, ptr %ptr 80 ret <16 x i8> %tmp1 81} 82 83define <8 x i16> @vld1Qi16(ptr %A) nounwind { 84;CHECK-LABEL: vld1Qi16: 85;Check the alignment value. Max for this instruction is 128 bits: 86;CHECK: vld1.16 {d16, d17}, [r0:128] 87 %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %A, i32 32) 88 ret <8 x i16> %tmp1 89} 90 91define <4 x i32> @vld1Qi32(ptr %A) nounwind { 92;CHECK-LABEL: vld1Qi32: 93;CHECK: vld1.32 94 %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr %A, i32 1) 95 ret <4 x i32> %tmp1 96} 97 98define <4 x float> @vld1Qf(ptr %A) nounwind { 99;CHECK-LABEL: vld1Qf: 100;CHECK: vld1.32 101 %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %A, i32 1) 102 ret <4 x float> %tmp1 103} 104 105define <2 x i64> @vld1Qi64(ptr %A) nounwind { 106;CHECK-LABEL: vld1Qi64: 107;CHECK: vld1.64 108 %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr %A, i32 1) 109 ret <2 x i64> %tmp1 110} 111 112define <2 x double> @vld1Qf64(ptr %A) nounwind { 113;CHECK-LABEL: vld1Qf64: 114;CHECK: vld1.64 115 %tmp1 = call <2 x double> @llvm.arm.neon.vld1.v2f64.p0(ptr %A, i32 1) 116 ret <2 x double> %tmp1 117} 118 119declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr, i32) nounwind readonly 120declare <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr, i32) nounwind readonly 121declare <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr, i32) nounwind readonly 122declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr, i32) nounwind readonly 123declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr, i32) nounwind readonly 124 125declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr, i32) nounwind readonly 126declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr, i32) nounwind readonly 127declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr, i32) nounwind readonly 128declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly 129declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr, i32) nounwind readonly 130declare <2 x double> @llvm.arm.neon.vld1.v2f64.p0(ptr, i32) nounwind readonly 131 132; Radar 8355607 133; Do not crash if the vld1 result is not used. 134define void @unused_vld1_result() { 135entry: 136 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) 137 call void @llvm.trap() 138 unreachable 139} 140 141declare void @llvm.trap() nounwind 142