1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=thumbv7-none-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-LE 3; RUN: llc < %s -mtriple=thumbebv7-none-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-BE 4 5define void @store_v8i8(ptr %ptr, <8 x i8> %val) { 6; CHECK-LABEL: store_v8i8: 7; CHECK: @ %bb.0: 8; CHECK-NEXT: ldr r0, [r0] 9; CHECK-NEXT: str r3, [r0, #4] 10; CHECK-NEXT: str r2, [r0] 11; CHECK-NEXT: bx lr 12 %A = load ptr, ptr %ptr 13 store <8 x i8> %val, ptr %A, align 1 14 ret void 15} 16 17define void @store_v8i8_update(ptr %ptr, <8 x i8> %val) { 18; CHECK-LE-LABEL: store_v8i8_update: 19; CHECK-LE: @ %bb.0: 20; CHECK-LE-NEXT: ldr r1, [r0] 21; CHECK-LE-NEXT: vmov d16, r2, r3 22; CHECK-LE-NEXT: vst1.8 {d16}, [r1]! 23; CHECK-LE-NEXT: str r1, [r0] 24; CHECK-LE-NEXT: bx lr 25; 26; CHECK-BE-LABEL: store_v8i8_update: 27; CHECK-BE: @ %bb.0: 28; CHECK-BE-NEXT: vmov d16, r3, r2 29; CHECK-BE-NEXT: ldr r1, [r0] 30; CHECK-BE-NEXT: vrev64.8 d16, d16 31; CHECK-BE-NEXT: vst1.8 {d16}, [r1]! 32; CHECK-BE-NEXT: str r1, [r0] 33; CHECK-BE-NEXT: bx lr 34 %A = load ptr, ptr %ptr 35 store <8 x i8> %val, ptr %A, align 1 36 %inc = getelementptr <8 x i8>, ptr %A, i38 1 37 store ptr %inc, ptr %ptr 38 ret void 39} 40 41define void @store_v4i16(ptr %ptr, <4 x i16> %val) { 42; CHECK-LABEL: store_v4i16: 43; CHECK: @ %bb.0: 44; CHECK-NEXT: ldr r0, [r0] 45; CHECK-NEXT: str r3, [r0, #4] 46; CHECK-NEXT: str r2, [r0] 47; CHECK-NEXT: bx lr 48 %A = load ptr, ptr %ptr 49 store <4 x i16> %val, ptr %A, align 1 50 ret void 51} 52 53define void @store_v4i16_update(ptr %ptr, <4 x i16> %val) { 54; CHECK-LE-LABEL: store_v4i16_update: 55; CHECK-LE: @ %bb.0: 56; CHECK-LE-NEXT: ldr r1, [r0] 57; CHECK-LE-NEXT: vmov d16, r2, r3 58; CHECK-LE-NEXT: vst1.8 {d16}, [r1]! 59; CHECK-LE-NEXT: str r1, [r0] 60; CHECK-LE-NEXT: bx lr 61; 62; CHECK-BE-LABEL: store_v4i16_update: 63; CHECK-BE: @ %bb.0: 64; CHECK-BE-NEXT: vmov d16, r3, r2 65; CHECK-BE-NEXT: ldr r1, [r0] 66; CHECK-BE-NEXT: vrev64.8 d16, d16 67; CHECK-BE-NEXT: vst1.8 {d16}, [r1]! 68; CHECK-BE-NEXT: str r1, [r0] 69; CHECK-BE-NEXT: bx lr 70 %A = load ptr, ptr %ptr 71 store <4 x i16> %val, ptr %A, align 1 72 %inc = getelementptr <4 x i16>, ptr %A, i34 1 73 store ptr %inc, ptr %ptr 74 ret void 75} 76 77define void @store_v2i32(ptr %ptr, <2 x i32> %val) { 78; CHECK-LABEL: store_v2i32: 79; CHECK: @ %bb.0: 80; CHECK-NEXT: ldr r0, [r0] 81; CHECK-NEXT: str r3, [r0, #4] 82; CHECK-NEXT: str r2, [r0] 83; CHECK-NEXT: bx lr 84 %A = load ptr, ptr %ptr 85 store <2 x i32> %val, ptr %A, align 1 86 ret void 87} 88 89define void @store_v2i32_update(ptr %ptr, <2 x i32> %val) { 90; CHECK-LE-LABEL: store_v2i32_update: 91; CHECK-LE: @ %bb.0: 92; CHECK-LE-NEXT: ldr r1, [r0] 93; CHECK-LE-NEXT: vmov d16, r2, r3 94; CHECK-LE-NEXT: vst1.8 {d16}, [r1]! 95; CHECK-LE-NEXT: str r1, [r0] 96; CHECK-LE-NEXT: bx lr 97; 98; CHECK-BE-LABEL: store_v2i32_update: 99; CHECK-BE: @ %bb.0: 100; CHECK-BE-NEXT: vmov d16, r3, r2 101; CHECK-BE-NEXT: ldr r1, [r0] 102; CHECK-BE-NEXT: vrev64.8 d16, d16 103; CHECK-BE-NEXT: vst1.8 {d16}, [r1]! 104; CHECK-BE-NEXT: str r1, [r0] 105; CHECK-BE-NEXT: bx lr 106 %A = load ptr, ptr %ptr 107 store <2 x i32> %val, ptr %A, align 1 108 %inc = getelementptr <2 x i32>, ptr %A, i32 1 109 store ptr %inc, ptr %ptr 110 ret void 111} 112 113define void @store_v2f32(ptr %ptr, <2 x float> %val) { 114; CHECK-LABEL: store_v2f32: 115; CHECK: @ %bb.0: 116; CHECK-NEXT: ldr r0, [r0] 117; CHECK-NEXT: str r3, [r0, #4] 118; CHECK-NEXT: str r2, [r0] 119; CHECK-NEXT: bx lr 120 %A = load ptr, ptr %ptr 121 store <2 x float> %val, ptr %A, align 1 122 ret void 123} 124 125define void @store_v2f32_update(ptr %ptr, <2 x float> %val) { 126; CHECK-LE-LABEL: store_v2f32_update: 127; CHECK-LE: @ %bb.0: 128; CHECK-LE-NEXT: ldr r1, [r0] 129; CHECK-LE-NEXT: vmov d16, r2, r3 130; CHECK-LE-NEXT: vst1.8 {d16}, [r1]! 131; CHECK-LE-NEXT: str r1, [r0] 132; CHECK-LE-NEXT: bx lr 133; 134; CHECK-BE-LABEL: store_v2f32_update: 135; CHECK-BE: @ %bb.0: 136; CHECK-BE-NEXT: vmov d16, r3, r2 137; CHECK-BE-NEXT: ldr r1, [r0] 138; CHECK-BE-NEXT: vrev64.8 d16, d16 139; CHECK-BE-NEXT: vst1.8 {d16}, [r1]! 140; CHECK-BE-NEXT: str r1, [r0] 141; CHECK-BE-NEXT: bx lr 142 %A = load ptr, ptr %ptr 143 store <2 x float> %val, ptr %A, align 1 144 %inc = getelementptr <2 x float>, ptr %A, i32 1 145 store ptr %inc, ptr %ptr 146 ret void 147} 148 149define void @store_v1i64(ptr %ptr, <1 x i64> %val) { 150; CHECK-LABEL: store_v1i64: 151; CHECK: @ %bb.0: 152; CHECK-NEXT: ldr r0, [r0] 153; CHECK-NEXT: str r3, [r0, #4] 154; CHECK-NEXT: str r2, [r0] 155; CHECK-NEXT: bx lr 156 %A = load ptr, ptr %ptr 157 store <1 x i64> %val, ptr %A, align 1 158 ret void 159} 160 161define void @store_v1i64_update(ptr %ptr, <1 x i64> %val) { 162; CHECK-LE-LABEL: store_v1i64_update: 163; CHECK-LE: @ %bb.0: 164; CHECK-LE-NEXT: ldr r1, [r0] 165; CHECK-LE-NEXT: vmov d16, r2, r3 166; CHECK-LE-NEXT: vst1.8 {d16}, [r1]! 167; CHECK-LE-NEXT: str r1, [r0] 168; CHECK-LE-NEXT: bx lr 169; 170; CHECK-BE-LABEL: store_v1i64_update: 171; CHECK-BE: @ %bb.0: 172; CHECK-BE-NEXT: vmov d16, r3, r2 173; CHECK-BE-NEXT: ldr r1, [r0] 174; CHECK-BE-NEXT: vrev64.8 d16, d16 175; CHECK-BE-NEXT: vst1.8 {d16}, [r1]! 176; CHECK-BE-NEXT: str r1, [r0] 177; CHECK-BE-NEXT: bx lr 178 %A = load ptr, ptr %ptr 179 store <1 x i64> %val, ptr %A, align 1 180 %inc = getelementptr <1 x i64>, ptr %A, i31 1 181 store ptr %inc, ptr %ptr 182 ret void 183} 184 185define void @store_v16i8(ptr %ptr, <16 x i8> %val) { 186; CHECK-LE-LABEL: store_v16i8: 187; CHECK-LE: @ %bb.0: 188; CHECK-LE-NEXT: vldr d17, [sp] 189; CHECK-LE-NEXT: ldr r0, [r0] 190; CHECK-LE-NEXT: vmov d16, r2, r3 191; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r0] 192; CHECK-LE-NEXT: bx lr 193; 194; CHECK-BE-LABEL: store_v16i8: 195; CHECK-BE: @ %bb.0: 196; CHECK-BE-NEXT: vldr d17, [sp] 197; CHECK-BE-NEXT: vmov d16, r3, r2 198; CHECK-BE-NEXT: ldr r0, [r0] 199; CHECK-BE-NEXT: vrev64.8 q8, q8 200; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r0] 201; CHECK-BE-NEXT: bx lr 202 %A = load ptr, ptr %ptr 203 store <16 x i8> %val, ptr %A, align 1 204 ret void 205} 206 207define void @store_v16i8_update(ptr %ptr, <16 x i8> %val) { 208; CHECK-LE-LABEL: store_v16i8_update: 209; CHECK-LE: @ %bb.0: 210; CHECK-LE-NEXT: vldr d17, [sp] 211; CHECK-LE-NEXT: vmov d16, r2, r3 212; CHECK-LE-NEXT: ldr r1, [r0] 213; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r1]! 214; CHECK-LE-NEXT: str r1, [r0] 215; CHECK-LE-NEXT: bx lr 216; 217; CHECK-BE-LABEL: store_v16i8_update: 218; CHECK-BE: @ %bb.0: 219; CHECK-BE-NEXT: vldr d17, [sp] 220; CHECK-BE-NEXT: vmov d16, r3, r2 221; CHECK-BE-NEXT: ldr r1, [r0] 222; CHECK-BE-NEXT: vrev64.8 q8, q8 223; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r1]! 224; CHECK-BE-NEXT: str r1, [r0] 225; CHECK-BE-NEXT: bx lr 226 %A = load ptr, ptr %ptr 227 store <16 x i8> %val, ptr %A, align 1 228 %inc = getelementptr <16 x i8>, ptr %A, i316 1 229 store ptr %inc, ptr %ptr 230 ret void 231} 232 233define void @store_v8i16(ptr %ptr, <8 x i16> %val) { 234; CHECK-LE-LABEL: store_v8i16: 235; CHECK-LE: @ %bb.0: 236; CHECK-LE-NEXT: vldr d17, [sp] 237; CHECK-LE-NEXT: ldr r0, [r0] 238; CHECK-LE-NEXT: vmov d16, r2, r3 239; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r0] 240; CHECK-LE-NEXT: bx lr 241; 242; CHECK-BE-LABEL: store_v8i16: 243; CHECK-BE: @ %bb.0: 244; CHECK-BE-NEXT: vldr d17, [sp] 245; CHECK-BE-NEXT: vmov d16, r3, r2 246; CHECK-BE-NEXT: ldr r0, [r0] 247; CHECK-BE-NEXT: vrev64.8 q8, q8 248; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r0] 249; CHECK-BE-NEXT: bx lr 250 %A = load ptr, ptr %ptr 251 store <8 x i16> %val, ptr %A, align 1 252 ret void 253} 254 255define void @store_v8i16_update(ptr %ptr, <8 x i16> %val) { 256; CHECK-LE-LABEL: store_v8i16_update: 257; CHECK-LE: @ %bb.0: 258; CHECK-LE-NEXT: vldr d17, [sp] 259; CHECK-LE-NEXT: vmov d16, r2, r3 260; CHECK-LE-NEXT: ldr r1, [r0] 261; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r1]! 262; CHECK-LE-NEXT: str r1, [r0] 263; CHECK-LE-NEXT: bx lr 264; 265; CHECK-BE-LABEL: store_v8i16_update: 266; CHECK-BE: @ %bb.0: 267; CHECK-BE-NEXT: vldr d17, [sp] 268; CHECK-BE-NEXT: vmov d16, r3, r2 269; CHECK-BE-NEXT: ldr r1, [r0] 270; CHECK-BE-NEXT: vrev64.8 q8, q8 271; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r1]! 272; CHECK-BE-NEXT: str r1, [r0] 273; CHECK-BE-NEXT: bx lr 274 %A = load ptr, ptr %ptr 275 store <8 x i16> %val, ptr %A, align 1 276 %inc = getelementptr <8 x i16>, ptr %A, i38 1 277 store ptr %inc, ptr %ptr 278 ret void 279} 280 281define void @store_v4i32(ptr %ptr, <4 x i32> %val) { 282; CHECK-LE-LABEL: store_v4i32: 283; CHECK-LE: @ %bb.0: 284; CHECK-LE-NEXT: vldr d17, [sp] 285; CHECK-LE-NEXT: ldr r0, [r0] 286; CHECK-LE-NEXT: vmov d16, r2, r3 287; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r0] 288; CHECK-LE-NEXT: bx lr 289; 290; CHECK-BE-LABEL: store_v4i32: 291; CHECK-BE: @ %bb.0: 292; CHECK-BE-NEXT: vldr d17, [sp] 293; CHECK-BE-NEXT: vmov d16, r3, r2 294; CHECK-BE-NEXT: ldr r0, [r0] 295; CHECK-BE-NEXT: vrev64.8 q8, q8 296; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r0] 297; CHECK-BE-NEXT: bx lr 298 %A = load ptr, ptr %ptr 299 store <4 x i32> %val, ptr %A, align 1 300 ret void 301} 302 303define void @store_v4i32_update(ptr %ptr, <4 x i32> %val) { 304; CHECK-LE-LABEL: store_v4i32_update: 305; CHECK-LE: @ %bb.0: 306; CHECK-LE-NEXT: vldr d17, [sp] 307; CHECK-LE-NEXT: vmov d16, r2, r3 308; CHECK-LE-NEXT: ldr r1, [r0] 309; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r1]! 310; CHECK-LE-NEXT: str r1, [r0] 311; CHECK-LE-NEXT: bx lr 312; 313; CHECK-BE-LABEL: store_v4i32_update: 314; CHECK-BE: @ %bb.0: 315; CHECK-BE-NEXT: vldr d17, [sp] 316; CHECK-BE-NEXT: vmov d16, r3, r2 317; CHECK-BE-NEXT: ldr r1, [r0] 318; CHECK-BE-NEXT: vrev64.8 q8, q8 319; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r1]! 320; CHECK-BE-NEXT: str r1, [r0] 321; CHECK-BE-NEXT: bx lr 322 %A = load ptr, ptr %ptr 323 store <4 x i32> %val, ptr %A, align 1 324 %inc = getelementptr <4 x i32>, ptr %A, i34 1 325 store ptr %inc, ptr %ptr 326 ret void 327} 328 329define void @store_v4f32(ptr %ptr, <4 x float> %val) { 330; CHECK-LE-LABEL: store_v4f32: 331; CHECK-LE: @ %bb.0: 332; CHECK-LE-NEXT: vldr d17, [sp] 333; CHECK-LE-NEXT: ldr r0, [r0] 334; CHECK-LE-NEXT: vmov d16, r2, r3 335; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r0] 336; CHECK-LE-NEXT: bx lr 337; 338; CHECK-BE-LABEL: store_v4f32: 339; CHECK-BE: @ %bb.0: 340; CHECK-BE-NEXT: vldr d17, [sp] 341; CHECK-BE-NEXT: vmov d16, r3, r2 342; CHECK-BE-NEXT: ldr r0, [r0] 343; CHECK-BE-NEXT: vrev64.8 q8, q8 344; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r0] 345; CHECK-BE-NEXT: bx lr 346 %A = load ptr, ptr %ptr 347 store <4 x float> %val, ptr %A, align 1 348 ret void 349} 350 351define void @store_v4f32_update(ptr %ptr, <4 x float> %val) { 352; CHECK-LE-LABEL: store_v4f32_update: 353; CHECK-LE: @ %bb.0: 354; CHECK-LE-NEXT: vldr d17, [sp] 355; CHECK-LE-NEXT: vmov d16, r2, r3 356; CHECK-LE-NEXT: ldr r1, [r0] 357; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r1]! 358; CHECK-LE-NEXT: str r1, [r0] 359; CHECK-LE-NEXT: bx lr 360; 361; CHECK-BE-LABEL: store_v4f32_update: 362; CHECK-BE: @ %bb.0: 363; CHECK-BE-NEXT: vldr d17, [sp] 364; CHECK-BE-NEXT: vmov d16, r3, r2 365; CHECK-BE-NEXT: ldr r1, [r0] 366; CHECK-BE-NEXT: vrev64.8 q8, q8 367; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r1]! 368; CHECK-BE-NEXT: str r1, [r0] 369; CHECK-BE-NEXT: bx lr 370 %A = load ptr, ptr %ptr 371 store <4 x float> %val, ptr %A, align 1 372 %inc = getelementptr <4 x float>, ptr %A, i34 1 373 store ptr %inc, ptr %ptr 374 ret void 375} 376 377define void @store_v2i64(ptr %ptr, <2 x i64> %val) { 378; CHECK-LE-LABEL: store_v2i64: 379; CHECK-LE: @ %bb.0: 380; CHECK-LE-NEXT: vldr d17, [sp] 381; CHECK-LE-NEXT: ldr r0, [r0] 382; CHECK-LE-NEXT: vmov d16, r2, r3 383; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r0] 384; CHECK-LE-NEXT: bx lr 385; 386; CHECK-BE-LABEL: store_v2i64: 387; CHECK-BE: @ %bb.0: 388; CHECK-BE-NEXT: vldr d17, [sp] 389; CHECK-BE-NEXT: vmov d16, r3, r2 390; CHECK-BE-NEXT: ldr r0, [r0] 391; CHECK-BE-NEXT: vrev64.8 q8, q8 392; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r0] 393; CHECK-BE-NEXT: bx lr 394 %A = load ptr, ptr %ptr 395 store <2 x i64> %val, ptr %A, align 1 396 ret void 397} 398 399define void @store_v2i64_update(ptr %ptr, <2 x i64> %val) { 400; CHECK-LE-LABEL: store_v2i64_update: 401; CHECK-LE: @ %bb.0: 402; CHECK-LE-NEXT: vldr d17, [sp] 403; CHECK-LE-NEXT: vmov d16, r2, r3 404; CHECK-LE-NEXT: ldr r1, [r0] 405; CHECK-LE-NEXT: vst1.8 {d16, d17}, [r1]! 406; CHECK-LE-NEXT: str r1, [r0] 407; CHECK-LE-NEXT: bx lr 408; 409; CHECK-BE-LABEL: store_v2i64_update: 410; CHECK-BE: @ %bb.0: 411; CHECK-BE-NEXT: vldr d17, [sp] 412; CHECK-BE-NEXT: vmov d16, r3, r2 413; CHECK-BE-NEXT: ldr r1, [r0] 414; CHECK-BE-NEXT: vrev64.8 q8, q8 415; CHECK-BE-NEXT: vst1.8 {d16, d17}, [r1]! 416; CHECK-BE-NEXT: str r1, [r0] 417; CHECK-BE-NEXT: bx lr 418 %A = load ptr, ptr %ptr 419 store <2 x i64> %val, ptr %A, align 1 420 %inc = getelementptr <2 x i64>, ptr %A, i32 1 421 store ptr %inc, ptr %ptr 422 ret void 423} 424 425define void @store_v2i64_update_aligned2(ptr %ptr, <2 x i64> %val) { 426; CHECK-LE-LABEL: store_v2i64_update_aligned2: 427; CHECK-LE: @ %bb.0: 428; CHECK-LE-NEXT: vldr d17, [sp] 429; CHECK-LE-NEXT: vmov d16, r2, r3 430; CHECK-LE-NEXT: ldr r1, [r0] 431; CHECK-LE-NEXT: vst1.16 {d16, d17}, [r1]! 432; CHECK-LE-NEXT: str r1, [r0] 433; CHECK-LE-NEXT: bx lr 434; 435; CHECK-BE-LABEL: store_v2i64_update_aligned2: 436; CHECK-BE: @ %bb.0: 437; CHECK-BE-NEXT: vldr d17, [sp] 438; CHECK-BE-NEXT: vmov d16, r3, r2 439; CHECK-BE-NEXT: ldr r1, [r0] 440; CHECK-BE-NEXT: vrev64.16 q8, q8 441; CHECK-BE-NEXT: vst1.16 {d16, d17}, [r1]! 442; CHECK-BE-NEXT: str r1, [r0] 443; CHECK-BE-NEXT: bx lr 444 %A = load ptr, ptr %ptr 445 store <2 x i64> %val, ptr %A, align 2 446 %inc = getelementptr <2 x i64>, ptr %A, i32 1 447 store ptr %inc, ptr %ptr 448 ret void 449} 450 451define void @store_v2i64_update_aligned4(ptr %ptr, <2 x i64> %val) { 452; CHECK-LE-LABEL: store_v2i64_update_aligned4: 453; CHECK-LE: @ %bb.0: 454; CHECK-LE-NEXT: vldr d17, [sp] 455; CHECK-LE-NEXT: vmov d16, r2, r3 456; CHECK-LE-NEXT: ldr r1, [r0] 457; CHECK-LE-NEXT: vst1.32 {d16, d17}, [r1]! 458; CHECK-LE-NEXT: str r1, [r0] 459; CHECK-LE-NEXT: bx lr 460; 461; CHECK-BE-LABEL: store_v2i64_update_aligned4: 462; CHECK-BE: @ %bb.0: 463; CHECK-BE-NEXT: vldr d17, [sp] 464; CHECK-BE-NEXT: vmov d16, r3, r2 465; CHECK-BE-NEXT: ldr r1, [r0] 466; CHECK-BE-NEXT: vrev64.32 q8, q8 467; CHECK-BE-NEXT: vst1.32 {d16, d17}, [r1]! 468; CHECK-BE-NEXT: str r1, [r0] 469; CHECK-BE-NEXT: bx lr 470 %A = load ptr, ptr %ptr 471 store <2 x i64> %val, ptr %A, align 4 472 %inc = getelementptr <2 x i64>, ptr %A, i32 1 473 store ptr %inc, ptr %ptr 474 ret void 475} 476 477define void @store_v2i64_update_aligned8(ptr %ptr, <2 x i64> %val) { 478; CHECK-LE-LABEL: store_v2i64_update_aligned8: 479; CHECK-LE: @ %bb.0: 480; CHECK-LE-NEXT: vldr d17, [sp] 481; CHECK-LE-NEXT: vmov d16, r2, r3 482; CHECK-LE-NEXT: ldr r1, [r0] 483; CHECK-LE-NEXT: vst1.64 {d16, d17}, [r1]! 484; CHECK-LE-NEXT: str r1, [r0] 485; CHECK-LE-NEXT: bx lr 486; 487; CHECK-BE-LABEL: store_v2i64_update_aligned8: 488; CHECK-BE: @ %bb.0: 489; CHECK-BE-NEXT: vldr d17, [sp] 490; CHECK-BE-NEXT: vmov d16, r3, r2 491; CHECK-BE-NEXT: ldr r1, [r0] 492; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r1]! 493; CHECK-BE-NEXT: str r1, [r0] 494; CHECK-BE-NEXT: bx lr 495 %A = load ptr, ptr %ptr 496 store <2 x i64> %val, ptr %A, align 8 497 %inc = getelementptr <2 x i64>, ptr %A, i32 1 498 store ptr %inc, ptr %ptr 499 ret void 500} 501 502define void @store_v2i64_update_aligned16(ptr %ptr, <2 x i64> %val) { 503; CHECK-LE-LABEL: store_v2i64_update_aligned16: 504; CHECK-LE: @ %bb.0: 505; CHECK-LE-NEXT: vldr d17, [sp] 506; CHECK-LE-NEXT: vmov d16, r2, r3 507; CHECK-LE-NEXT: ldr r1, [r0] 508; CHECK-LE-NEXT: vst1.64 {d16, d17}, [r1:128]! 509; CHECK-LE-NEXT: str r1, [r0] 510; CHECK-LE-NEXT: bx lr 511; 512; CHECK-BE-LABEL: store_v2i64_update_aligned16: 513; CHECK-BE: @ %bb.0: 514; CHECK-BE-NEXT: vldr d17, [sp] 515; CHECK-BE-NEXT: vmov d16, r3, r2 516; CHECK-BE-NEXT: ldr r1, [r0] 517; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r1:128]! 518; CHECK-BE-NEXT: str r1, [r0] 519; CHECK-BE-NEXT: bx lr 520 %A = load ptr, ptr %ptr 521 store <2 x i64> %val, ptr %A, align 16 522 %inc = getelementptr <2 x i64>, ptr %A, i32 1 523 store ptr %inc, ptr %ptr 524 ret void 525} 526 527define void @truncstore_v4i32tov4i8(ptr %ptr, <4 x i32> %val) { 528; CHECK-LE-LABEL: truncstore_v4i32tov4i8: 529; CHECK-LE: @ %bb.0: 530; CHECK-LE-NEXT: vldr d17, [sp] 531; CHECK-LE-NEXT: vmov d16, r2, r3 532; CHECK-LE-NEXT: ldr r0, [r0] 533; CHECK-LE-NEXT: vmovn.i32 d16, q8 534; CHECK-LE-NEXT: vuzp.8 d16, d17 535; CHECK-LE-NEXT: vst1.32 {d16[0]}, [r0:32] 536; CHECK-LE-NEXT: bx lr 537; 538; CHECK-BE-LABEL: truncstore_v4i32tov4i8: 539; CHECK-BE: @ %bb.0: 540; CHECK-BE-NEXT: vldr d17, [sp] 541; CHECK-BE-NEXT: vmov d16, r3, r2 542; CHECK-BE-NEXT: vrev64.32 q8, q8 543; CHECK-BE-NEXT: vmovn.i32 d16, q8 544; CHECK-BE-NEXT: vrev16.8 d16, d16 545; CHECK-BE-NEXT: vuzp.8 d16, d17 546; CHECK-BE-NEXT: ldr r0, [r0] 547; CHECK-BE-NEXT: vrev32.8 d16, d17 548; CHECK-BE-NEXT: vst1.32 {d16[0]}, [r0:32] 549; CHECK-BE-NEXT: bx lr 550 %A = load ptr, ptr %ptr 551 %trunc = trunc <4 x i32> %val to <4 x i8> 552 store <4 x i8> %trunc, ptr %A, align 4 553 ret void 554} 555 556define void @truncstore_v4i32tov4i8_fake_update(ptr %ptr, <4 x i32> %val) { 557; CHECK-LE-LABEL: truncstore_v4i32tov4i8_fake_update: 558; CHECK-LE: @ %bb.0: 559; CHECK-LE-NEXT: vldr d17, [sp] 560; CHECK-LE-NEXT: vmov d16, r2, r3 561; CHECK-LE-NEXT: ldr r1, [r0] 562; CHECK-LE-NEXT: movs r2, #16 563; CHECK-LE-NEXT: vmovn.i32 d16, q8 564; CHECK-LE-NEXT: vuzp.8 d16, d17 565; CHECK-LE-NEXT: vst1.32 {d16[0]}, [r1:32], r2 566; CHECK-LE-NEXT: str r1, [r0] 567; CHECK-LE-NEXT: bx lr 568; 569; CHECK-BE-LABEL: truncstore_v4i32tov4i8_fake_update: 570; CHECK-BE: @ %bb.0: 571; CHECK-BE-NEXT: vldr d17, [sp] 572; CHECK-BE-NEXT: vmov d16, r3, r2 573; CHECK-BE-NEXT: movs r2, #16 574; CHECK-BE-NEXT: vrev64.32 q8, q8 575; CHECK-BE-NEXT: vmovn.i32 d16, q8 576; CHECK-BE-NEXT: vrev16.8 d16, d16 577; CHECK-BE-NEXT: vuzp.8 d16, d17 578; CHECK-BE-NEXT: ldr r1, [r0] 579; CHECK-BE-NEXT: vrev32.8 d16, d17 580; CHECK-BE-NEXT: vst1.32 {d16[0]}, [r1:32], r2 581; CHECK-BE-NEXT: str r1, [r0] 582; CHECK-BE-NEXT: bx lr 583 %A = load ptr, ptr %ptr 584 %trunc = trunc <4 x i32> %val to <4 x i8> 585 store <4 x i8> %trunc, ptr %A, align 4 586 %inc = getelementptr <4 x i8>, ptr %A, i38 4 587 store ptr %inc, ptr %ptr 588 ret void 589} 590 591define ptr @test_vst1_1reg(ptr %ptr.in, ptr %ptr.out) { 592; CHECK-LE-LABEL: test_vst1_1reg: 593; CHECK-LE: @ %bb.0: 594; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 595; CHECK-LE-NEXT: movs r0, #32 596; CHECK-LE-NEXT: vst1.32 {d16, d17}, [r1], r0 597; CHECK-LE-NEXT: mov r0, r1 598; CHECK-LE-NEXT: bx lr 599; 600; CHECK-BE-LABEL: test_vst1_1reg: 601; CHECK-BE: @ %bb.0: 602; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 603; CHECK-BE-NEXT: movs r0, #32 604; CHECK-BE-NEXT: vrev64.32 q8, q8 605; CHECK-BE-NEXT: vst1.32 {d16, d17}, [r1], r0 606; CHECK-BE-NEXT: mov r0, r1 607; CHECK-BE-NEXT: bx lr 608 %val = load <4 x i32>, ptr %ptr.in 609 store <4 x i32> %val, ptr %ptr.out 610 %next = getelementptr <4 x i32>, ptr %ptr.out, i32 2 611 ret ptr %next 612} 613 614; PR56970 615define void @v3i8store(ptr %p) { 616; CHECK-LE-LABEL: v3i8store: 617; CHECK-LE: @ %bb.0: 618; CHECK-LE-NEXT: .pad #4 619; CHECK-LE-NEXT: sub sp, #4 620; CHECK-LE-NEXT: movs r1, #0 621; CHECK-LE-NEXT: mov r2, sp 622; CHECK-LE-NEXT: str r1, [sp] 623; CHECK-LE-NEXT: vld1.32 {d16[0]}, [r2:32] 624; CHECK-LE-NEXT: strb r1, [r0, #2] 625; CHECK-LE-NEXT: vmovl.u16 q8, d16 626; CHECK-LE-NEXT: vmov.32 r2, d16[0] 627; CHECK-LE-NEXT: strh r2, [r0] 628; CHECK-LE-NEXT: add sp, #4 629; CHECK-LE-NEXT: bx lr 630; 631; CHECK-BE-LABEL: v3i8store: 632; CHECK-BE: @ %bb.0: 633; CHECK-BE-NEXT: .pad #4 634; CHECK-BE-NEXT: sub sp, #4 635; CHECK-BE-NEXT: movs r1, #0 636; CHECK-BE-NEXT: mov r2, sp 637; CHECK-BE-NEXT: str r1, [sp] 638; CHECK-BE-NEXT: vld1.32 {d16[0]}, [r2:32] 639; CHECK-BE-NEXT: strb r1, [r0, #2] 640; CHECK-BE-NEXT: vrev32.16 d16, d16 641; CHECK-BE-NEXT: vmovl.u16 q8, d16 642; CHECK-BE-NEXT: vmov.32 r2, d16[0] 643; CHECK-BE-NEXT: strh r2, [r0] 644; CHECK-BE-NEXT: add sp, #4 645; CHECK-BE-NEXT: bx lr 646 store <3 x i8> zeroinitializer, ptr %p, align 4 647 ret void 648} 649 650define void @v3i64shuffle(ptr %p, <3 x i64> %a) { 651; CHECK-LE-LABEL: v3i64shuffle: 652; CHECK-LE: @ %bb.0: 653; CHECK-LE-NEXT: vmov.i32 q8, #0x0 654; CHECK-LE-NEXT: ldrd r12, r1, [sp, #8] 655; CHECK-LE-NEXT: vmov d18, r2, r3 656; CHECK-LE-NEXT: vorr d19, d16, d16 657; CHECK-LE-NEXT: str r1, [r0, #20] 658; CHECK-LE-NEXT: vst1.32 {d18, d19}, [r0]! 659; CHECK-LE-NEXT: str.w r12, [r0] 660; CHECK-LE-NEXT: bx lr 661; 662; CHECK-BE-LABEL: v3i64shuffle: 663; CHECK-BE: @ %bb.0: 664; CHECK-BE-NEXT: vldr d16, [sp, #8] 665; CHECK-BE-NEXT: vmov.i32 q9, #0x0 666; CHECK-BE-NEXT: vrev64.32 q8, q8 667; CHECK-BE-NEXT: vmov r12, r1, d16 668; CHECK-BE-NEXT: vmov d16, r3, r2 669; CHECK-BE-NEXT: vorr d17, d18, d18 670; CHECK-BE-NEXT: vrev64.32 q8, q8 671; CHECK-BE-NEXT: str r1, [r0, #20] 672; CHECK-BE-NEXT: vst1.32 {d16, d17}, [r0]! 673; CHECK-BE-NEXT: str.w r12, [r0] 674; CHECK-BE-NEXT: bx lr 675 %b = shufflevector <3 x i64> %a, <3 x i64> zeroinitializer, <3 x i32> <i32 0, i32 3, i32 2> 676 store <3 x i64> %b, ptr %p, align 4 677 ret void 678} 679 680