xref: /llvm-project/llvm/test/CodeGen/ARM/vector-extract.ll (revision bed1c7f061aa12417aa081e334afdba45767b938)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=armv7a-none-eabi -mattr=+neon %s -o - | FileCheck %s
3
4; Check that the two extracts are not combined into a vmov.
5
6%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
7
8define i32 @vld4Qi32(ptr %A) nounwind {
9; CHECK-LABEL: vld4Qi32:
10; CHECK:       @ %bb.0:
11; CHECK-NEXT:    vld4.32 {d16, d18, d20, d22}, [r0]!
12; CHECK-NEXT:    vld4.32 {d17, d19, d21, d23}, [r0]
13; CHECK-NEXT:    vmov.32 r0, d18[1]
14; CHECK-NEXT:    vmov.32 r1, d16[0]
15; CHECK-NEXT:    add r0, r1, r0
16; CHECK-NEXT:    bx lr
17        %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr %A, i32 1)
18        %tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0
19        %tmp3 = extractelement <4 x i32> %tmp2, i32 0
20        %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 1
21        %tmp5 = extractelement <4 x i32> %tmp4, i32 1
22        %tmp6 = add i32 %tmp3, %tmp5
23        ret i32 %tmp6
24}
25
26declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr, i32) nounwind readonly
27