1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=armv7-none-eabi | FileCheck %s 3 4; PR7158 5define i32 @test_pr7158() nounwind { 6; CHECK-LABEL: test_pr7158: 7; CHECK: @ %bb.0: @ %bb.nph55.bb.nph55.split_crit_edge 8; CHECK-NEXT: .LBB0_1: @ %bb.i19 9; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 10; CHECK-NEXT: b .LBB0_1 11bb.nph55.bb.nph55.split_crit_edge: 12 br label %bb3 13 14bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge 15 br i1 undef, label %bb.i19, label %bb3 16 17bb.i19: ; preds = %bb.i19, %bb3 18 %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3] 19 %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1] 20 %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0] 21 %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0] 22 br label %bb.i19 23} 24 25; Check that the DAG combiner does not arbitrarily modify BUILD_VECTORs 26; after legalization. 27define void @test_illegal_build_vector() nounwind { 28; CHECK-LABEL: test_illegal_build_vector: 29; CHECK: @ %bb.0: @ %entry 30entry: 31 store <2 x i64> undef, ptr undef, align 16 32 %0 = load <16 x i8>, ptr undef, align 16 ; <<16 x i8>> [#uses=1] 33 %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] 34 store <16 x i8> %1, ptr undef, align 16 35 ret void 36} 37 38; PR22678 39; Check CONCAT_VECTORS DAG combiner pass doesn't introduce illegal types. 40define void @test_pr22678() { 41; CHECK-LABEL: test_pr22678: 42; CHECK: @ %bb.0: 43 %1 = fptoui <16 x float> undef to <16 x i8> 44 store <16 x i8> %1, ptr undef 45 ret void 46} 47 48; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is 49; converted back to be used as a vector type. 50define <4 x i32> @test_vmovrrd_combine() nounwind { 51; CHECK-LABEL: test_vmovrrd_combine: 52; CHECK: @ %bb.0: @ %entry 53; CHECK-NEXT: mov r0, #0 54; CHECK-NEXT: cmp r0, #0 55; CHECK-NEXT: @ implicit-def: $q8 56; CHECK-NEXT: bne .LBB3_2 57; CHECK-NEXT: @ %bb.1: @ %bb1.preheader 58; CHECK-NEXT: vmov.i32 q8, #0x0 59; CHECK-NEXT: .LBB3_2: @ %bb2 60; CHECK-NEXT: vmov r0, r1, d16 61; CHECK-NEXT: vmov r2, r3, d17 62; CHECK-NEXT: bx lr 63entry: 64 br i1 undef, label %bb1, label %bb2 65 66bb1: 67 %0 = bitcast <2 x i64> zeroinitializer to <2 x double> 68 %1 = extractelement <2 x double> %0, i32 0 69 %2 = bitcast double %1 to i64 70 %3 = insertelement <1 x i64> undef, i64 %2, i32 0 71 %4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> <i32 0, i32 1> 72 %tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8> 73 %5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19> 74 %tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32> 75 br i1 undef, label %bb2, label %bb1 76 77bb2: 78 %result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ] 79 ret <4 x i32> %result 80} 81 82; Test trying to do a ShiftCombine on illegal types. 83; The vector should be split first. 84define void @lshrIllegalType(ptr %A) nounwind { 85; CHECK-LABEL: lshrIllegalType: 86; CHECK: @ %bb.0: 87; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128] 88; CHECK-NEXT: vshr.u32 q8, q8, #3 89; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]! 90; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128] 91; CHECK-NEXT: vshr.u32 q8, q8, #3 92; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] 93; CHECK-NEXT: bx lr 94 %tmp1 = load <8 x i32>, ptr %A 95 %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 96 store <8 x i32> %tmp2, ptr %A 97 ret void 98} 99 100; Test folding a binary vector operation with constant BUILD_VECTOR 101; operands with i16 elements. 102define void @test_i16_constant_fold() nounwind optsize { 103; CHECK-LABEL: test_i16_constant_fold: 104; CHECK: @ %bb.0: @ %entry 105; CHECK-NEXT: vmov.i8 d16, #0x1 106; CHECK-NEXT: vst1.8 {d16}, [r0] 107; CHECK-NEXT: bx lr 108entry: 109 %0 = sext <4 x i1> zeroinitializer to <4 x i16> 110 %1 = add <4 x i16> %0, zeroinitializer 111 %2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 112 %3 = add <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 113 %4 = trunc <8 x i16> %3 to <8 x i8> 114 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr undef, <8 x i8> %4, i32 1) 115 ret void 116} 117 118declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind 119 120; Test that loads and stores of i64 vector elements are handled as f64 values 121; so they are not split up into i32 values. Radar 8755338. 122define void @i64_buildvector(ptr %ptr, ptr %vp) nounwind { 123; CHECK-LABEL: i64_buildvector: 124; CHECK: @ %bb.0: 125; CHECK-NEXT: vldr d16, [r0] 126; CHECK-NEXT: vst1.64 {d16, d17}, [r1] 127; CHECK-NEXT: bx lr 128 %t0 = load i64, ptr %ptr, align 4 129 %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0 130 store <2 x i64> %t1, ptr %vp 131 ret void 132} 133 134define void @i64_insertelement(ptr %ptr, ptr %vp) nounwind { 135; CHECK-LABEL: i64_insertelement: 136; CHECK: @ %bb.0: 137; CHECK-NEXT: ldm r0, {r0, r3} 138; CHECK-NEXT: stm r1, {r0, r3} 139; CHECK-NEXT: bx lr 140 %t0 = load i64, ptr %ptr, align 4 141 %vec = load <2 x i64>, ptr %vp 142 %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0 143 store <2 x i64> %t1, ptr %vp 144 ret void 145} 146 147define void @i64_extractelement(ptr %ptr, ptr %vp) nounwind { 148; CHECK-LABEL: i64_extractelement: 149; CHECK: @ %bb.0: 150; CHECK-NEXT: vldr d16, [r1] 151; CHECK-NEXT: vstr d16, [r0] 152; CHECK-NEXT: bx lr 153 %vec = load <2 x i64>, ptr %vp 154 %t1 = extractelement <2 x i64> %vec, i32 0 155 store i64 %t1, ptr %ptr 156 ret void 157} 158 159; Test trying to do a AND Combine on illegal types. 160define void @andVec(ptr %A) nounwind { 161; CHECK-LABEL: andVec: 162; CHECK: @ %bb.0: 163; CHECK-NEXT: .pad #8 164; CHECK-NEXT: sub sp, sp, #8 165; CHECK-NEXT: ldr r1, [r0] 166; CHECK-NEXT: vmov.i16 d17, #0x7 167; CHECK-NEXT: str r1, [sp, #4] 168; CHECK-NEXT: add r1, sp, #4 169; CHECK-NEXT: vld1.32 {d16[0]}, [r1:32] 170; CHECK-NEXT: mov r1, sp 171; CHECK-NEXT: vmovl.u8 q9, d16 172; CHECK-NEXT: vand d16, d18, d17 173; CHECK-NEXT: vorr d17, d16, d16 174; CHECK-NEXT: vuzp.8 d17, d18 175; CHECK-NEXT: vst1.32 {d17[0]}, [r1:32] 176; CHECK-NEXT: vld1.32 {d17[0]}, [r1:32] 177; CHECK-NEXT: vmov.u16 r1, d16[2] 178; CHECK-NEXT: vmovl.u16 q8, d17 179; CHECK-NEXT: vmov.32 r2, d16[0] 180; CHECK-NEXT: strb r1, [r0, #2] 181; CHECK-NEXT: strh r2, [r0] 182; CHECK-NEXT: add sp, sp, #8 183; CHECK-NEXT: bx lr 184 %tmp = load <3 x i8>, ptr %A, align 4 185 %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7> 186 store <3 x i8> %and, ptr %A 187 ret void 188} 189 190 191; Test trying to do an OR Combine on illegal types. 192define void @orVec(ptr %A) nounwind { 193; CHECK-LABEL: orVec: 194; CHECK: @ %bb.0: 195; CHECK-NEXT: .pad #8 196; CHECK-NEXT: sub sp, sp, #8 197; CHECK-NEXT: ldr r1, [r0] 198; CHECK-NEXT: str r1, [sp, #4] 199; CHECK-NEXT: add r1, sp, #4 200; CHECK-NEXT: vld1.32 {d16[0]}, [r1:32] 201; CHECK-NEXT: mov r1, sp 202; CHECK-NEXT: vmovl.u8 q8, d16 203; CHECK-NEXT: vorr.i16 d16, #0x7 204; CHECK-NEXT: vorr d18, d16, d16 205; CHECK-NEXT: vuzp.8 d18, d19 206; CHECK-NEXT: vst1.32 {d18[0]}, [r1:32] 207; CHECK-NEXT: vld1.32 {d18[0]}, [r1:32] 208; CHECK-NEXT: vmov.u16 r1, d16[2] 209; CHECK-NEXT: vmovl.u16 q8, d18 210; CHECK-NEXT: vmov.32 r2, d16[0] 211; CHECK-NEXT: strb r1, [r0, #2] 212; CHECK-NEXT: strh r2, [r0] 213; CHECK-NEXT: add sp, sp, #8 214; CHECK-NEXT: bx lr 215 %tmp = load <3 x i8>, ptr %A, align 4 216 %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7> 217 store <3 x i8> %or, ptr %A 218 ret void 219} 220 221; The following test was hitting an assertion in the DAG combiner when 222; constant folding the multiply because the "sext undef" was translated to 223; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands 224; of the other BUILD_VECTOR. 225define i16 @foldBuildVectors() { 226; CHECK-LABEL: foldBuildVectors: 227; CHECK: @ %bb.0: 228; CHECK-NEXT: mov r0, #0 229; CHECK-NEXT: bx lr 230 %1 = sext <8 x i8> undef to <8 x i16> 231 %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 232 %3 = extractelement <8 x i16> %2, i32 0 233 ret i16 %3 234} 235 236; Test that we are generating vrev and vext for reverse shuffles of v8i16 237; shuffles. 238define void @reverse_v8i16(ptr %loadaddr, ptr %storeaddr) { 239; CHECK-LABEL: reverse_v8i16: 240; CHECK: @ %bb.0: 241; CHECK-NEXT: vld1.64 {d16, d17}, [r0] 242; CHECK-NEXT: vrev64.16 q8, q8 243; CHECK-NEXT: vext.16 q8, q8, q8, #4 244; CHECK-NEXT: vst1.64 {d16, d17}, [r1] 245; CHECK-NEXT: bx lr 246 %v0 = load <8 x i16>, ptr %loadaddr 247 %v1 = shufflevector <8 x i16> %v0, <8 x i16> undef, 248 <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 249 store <8 x i16> %v1, ptr %storeaddr 250 ret void 251} 252 253; Test that we are generating vrev and vext for reverse shuffles of v16i8 254; shuffles. 255define void @reverse_v16i8(ptr %loadaddr, ptr %storeaddr) { 256; CHECK-LABEL: reverse_v16i8: 257; CHECK: @ %bb.0: 258; CHECK-NEXT: vld1.64 {d16, d17}, [r0] 259; CHECK-NEXT: vrev64.8 q8, q8 260; CHECK-NEXT: vext.8 q8, q8, q8, #8 261; CHECK-NEXT: vst1.64 {d16, d17}, [r1] 262; CHECK-NEXT: bx lr 263 %v0 = load <16 x i8>, ptr %loadaddr 264 %v1 = shufflevector <16 x i8> %v0, <16 x i8> undef, 265 <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, 266 i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 267 store <16 x i8> %v1, ptr %storeaddr 268 ret void 269} 270 271; <rdar://problem/14170854>. 272; vldr cannot handle unaligned loads. 273; Fall back to vld1.32, which can, instead of using the general purpose loads 274; followed by a costly sequence of instructions to build the vector register. 275define <8 x i16> @t3(i8 zeroext %xf, ptr nocapture %sp0, ptr nocapture %sp1, ptr nocapture %outp) { 276; CHECK-LABEL: t3: 277; CHECK: @ %bb.0: @ %entry 278; CHECK-NEXT: vld1.32 {d16[0]}, [r1] 279; CHECK-NEXT: vld1.32 {d16[1]}, [r2] 280; CHECK-NEXT: vmull.u8 q8, d16, d16 281; CHECK-NEXT: vmov r0, r1, d16 282; CHECK-NEXT: vmov r2, r3, d17 283; CHECK-NEXT: bx lr 284entry: 285 %pix_sp0.0.copyload = load i32, ptr %sp0, align 1 286 %pix_sp1.0.copyload = load i32, ptr %sp1, align 1 287 %vecinit = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 288 %vecinit1 = insertelement <2 x i32> %vecinit, i32 %pix_sp1.0.copyload, i32 1 289 %0 = bitcast <2 x i32> %vecinit1 to <8 x i8> 290 %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0) 291 ret <8 x i16> %vmull.i 292} 293 294; Function Attrs: nounwind readnone 295declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) 296 297; Check that (insert_vector_elt (load)) => (vector_load). 298; Thus, check that scalar_to_vector do not interfer with that. 299define <8 x i16> @t4(ptr nocapture %sp0) { 300; CHECK-LABEL: t4: 301; CHECK: @ %bb.0: @ %entry 302; CHECK-NEXT: vld1.32 {d16[0]}, [r0] 303; CHECK-NEXT: vmull.u8 q8, d16, d16 304; CHECK-NEXT: vmov r0, r1, d16 305; CHECK-NEXT: vmov r2, r3, d17 306; CHECK-NEXT: bx lr 307entry: 308 %pix_sp0.0.copyload = load i32, ptr %sp0, align 1 309 %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 310 %0 = bitcast <2 x i32> %vec to <8 x i8> 311 %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0) 312 ret <8 x i16> %vmull.i 313} 314 315; Make sure vector load is used for all three loads. 316; Lowering to build vector was breaking the single use property of the load of 317; %pix_sp0.0.copyload. 318define <8 x i16> @t5(ptr nocapture %sp0, ptr nocapture %sp1, ptr nocapture %sp2) { 319; CHECK-LABEL: t5: 320; CHECK: @ %bb.0: @ %entry 321; CHECK-NEXT: vld1.32 {d16[1]}, [r0] 322; CHECK-NEXT: vorr d17, d16, d16 323; CHECK-NEXT: vld1.32 {d16[0]}, [r1] 324; CHECK-NEXT: vld1.32 {d17[0]}, [r2] 325; CHECK-NEXT: vmull.u8 q8, d16, d17 326; CHECK-NEXT: vmov r0, r1, d16 327; CHECK-NEXT: vmov r2, r3, d17 328; CHECK-NEXT: bx lr 329entry: 330 %pix_sp0.0.copyload = load i32, ptr %sp0, align 1 331 %pix_sp1.0.copyload = load i32, ptr %sp1, align 1 332 %pix_sp2.0.copyload = load i32, ptr %sp2, align 1 333 %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 1 334 %vecinit1 = insertelement <2 x i32> %vec, i32 %pix_sp1.0.copyload, i32 0 335 %vecinit2 = insertelement <2 x i32> %vec, i32 %pix_sp2.0.copyload, i32 0 336 %0 = bitcast <2 x i32> %vecinit1 to <8 x i8> 337 %1 = bitcast <2 x i32> %vecinit2 to <8 x i8> 338 %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %1) 339 ret <8 x i16> %vmull.i 340} 341 342; <rdar://problem/14989896> Make sure we manage to truncate a vector from an 343; illegal type to a legal type. 344define <2 x i8> @test_truncate(<2 x i128> %in) { 345; CHECK-LABEL: test_truncate: 346; CHECK: @ %bb.0: @ %entry 347; CHECK-NEXT: vmov.32 d16[0], r0 348; CHECK-NEXT: mov r0, sp 349; CHECK-NEXT: vld1.32 {d16[1]}, [r0:32] 350; CHECK-NEXT: vmov r0, r1, d16 351; CHECK-NEXT: bx lr 352entry: 353 %res = trunc <2 x i128> %in to <2 x i8> 354 ret <2 x i8> %res 355} 356