xref: /llvm-project/llvm/test/CodeGen/ARM/uxtb.ll (revision 0a9688594062b6303aa89ad0775c9814da8d1a1e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple armv6-- -filetype asm -o - %s | FileCheck %s
3
4define i32 @test1(i32 %x) {
5; CHECK-LABEL: test1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    uxtb16 r0, r0
8; CHECK-NEXT:    bx lr
9  %tmp1 = and i32 %x, 16711935
10  ret i32 %tmp1
11}
12
13define i32 @test2(i32 %x) {
14; CHECK-LABEL: test2:
15; CHECK:       @ %bb.0:
16; CHECK-NEXT:    uxtb16 r0, r0, ror #8
17; CHECK-NEXT:    bx lr
18  %tmp1 = lshr i32 %x, 8
19  %tmp2 = and i32 %tmp1, 16711935
20  ret i32 %tmp2
21}
22
23define i32 @test3(i32 %x) {
24; CHECK-LABEL: test3:
25; CHECK:       @ %bb.0:
26; CHECK-NEXT:    uxtb16 r0, r0, ror #8
27; CHECK-NEXT:    bx lr
28  %tmp1 = lshr i32 %x, 8
29  %tmp2 = and i32 %tmp1, 16711935
30  ret i32 %tmp2
31}
32
33define i32 @test4(i32 %x) {
34; CHECK-LABEL: test4:
35; CHECK:       @ %bb.0:
36; CHECK-NEXT:    uxtb16 r0, r0, ror #8
37; CHECK-NEXT:    bx lr
38  %tmp1 = lshr i32 %x, 8
39  %tmp6 = and i32 %tmp1, 16711935
40  ret i32 %tmp6
41}
42
43define i32 @test5(i32 %x) {
44; CHECK-LABEL: test5:
45; CHECK:       @ %bb.0:
46; CHECK-NEXT:    uxtb16 r0, r0, ror #8
47; CHECK-NEXT:    bx lr
48  %tmp1 = lshr i32 %x, 8
49  %tmp2 = and i32 %tmp1, 16711935
50  ret i32 %tmp2
51}
52
53define i32 @test6(i32 %x) {
54; CHECK-LABEL: test6:
55; CHECK:       @ %bb.0:
56; CHECK-NEXT:    uxtb16 r0, r0, ror #16
57; CHECK-NEXT:    bx lr
58  %tmp1 = lshr i32 %x, 16
59  %tmp2 = and i32 %tmp1, 255
60  %tmp4 = shl i32 %x, 16
61  %tmp5 = and i32 %tmp4, 16711680
62  %tmp6 = or i32 %tmp2, %tmp5
63  ret i32 %tmp6
64}
65
66define i32 @test7(i32 %x) {
67; CHECK-LABEL: test7:
68; CHECK:       @ %bb.0:
69; CHECK-NEXT:    uxtb16 r0, r0, ror #16
70; CHECK-NEXT:    bx lr
71  %tmp1 = lshr i32 %x, 16
72  %tmp2 = and i32 %tmp1, 255
73  %tmp4 = shl i32 %x, 16
74  %tmp5 = and i32 %tmp4, 16711680
75  %tmp6 = or i32 %tmp2, %tmp5
76  ret i32 %tmp6
77}
78
79define i32 @test8(i32 %x) {
80; CHECK-LABEL: test8:
81; CHECK:       @ %bb.0:
82; CHECK-NEXT:    uxtb16 r0, r0, ror #24
83; CHECK-NEXT:    bx lr
84  %tmp1 = shl i32 %x, 8
85  %tmp2 = and i32 %tmp1, 16711680
86  %tmp5 = lshr i32 %x, 24
87  %tmp6 = or i32 %tmp2, %tmp5
88  ret i32 %tmp6
89}
90
91define i32 @test9(i32 %x) {
92; CHECK-LABEL: test9:
93; CHECK:       @ %bb.0:
94; CHECK-NEXT:    uxtb16 r0, r0, ror #24
95; CHECK-NEXT:    bx lr
96  %tmp1 = lshr i32 %x, 24
97  %tmp4 = shl i32 %x, 8
98  %tmp5 = and i32 %tmp4, 16711680
99  %tmp6 = or i32 %tmp5, %tmp1
100  ret i32 %tmp6
101}
102
103; FIXME: Failed to match uxtb16
104define i32 @test10(i32 %p0) {
105; CHECK-LABEL: test10:
106; CHECK:       @ %bb.0:
107; CHECK-NEXT:    mov r1, #248
108; CHECK-NEXT:    mov r2, #7
109; CHECK-NEXT:    orr r1, r1, #16252928
110; CHECK-NEXT:    orr r2, r2, #458752
111; CHECK-NEXT:    and r1, r1, r0, lsr #7
112; CHECK-NEXT:    and r0, r2, r0, lsr #12
113; CHECK-NEXT:    orr r0, r0, r1
114; CHECK-NEXT:    bx lr
115  %tmp1 = lshr i32 %p0, 7
116  %tmp2 = and i32 %tmp1, 16253176
117  %tmp4 = lshr i32 %p0, 12
118  %tmp5 = and i32 %tmp4, 458759
119  %tmp7 = or i32 %tmp5, %tmp2
120  ret i32 %tmp7
121}
122
123define i32 @test11(i32 %p0) {
124; CHECK-LABEL: test11:
125; CHECK:       @ %bb.0:
126; CHECK-NEXT:    mov r1, #1
127; CHECK-NEXT:    and r0, r0, #3
128; CHECK-NEXT:    orr r1, r1, #65536
129; CHECK-NEXT:    lsl r0, r1, r0
130; CHECK-NEXT:    lsr r0, r0, #1
131; CHECK-NEXT:    uxtb16 r0, r0
132; CHECK-NEXT:    bx lr
133  %p = and i32 %p0, 3
134  %a = shl i32 65537, %p
135  %b = lshr i32 %a, 1
136  %tmp7 = and i32 %b, 458759
137  ret i32 %tmp7
138}
139