xref: /llvm-project/llvm/test/CodeGen/ARM/unsafe-fneg-select-minnum-maxnum-combine.ll (revision 65420c8041f4ca44a3a14c5f7faf426ee6a7c6a4) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-- -mattr=+fullfp16 < %s | FileCheck %s
3
4define float @select_fneg_a_or_8_cmp_olt_a_neg8_f32(float %a, float %b) #0 {
5; CHECK-LABEL: select_fneg_a_or_8_cmp_olt_a_neg8_f32:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    vmov.f32 s0, #-8.000000e+00
8; CHECK-NEXT:    vmov s2, r0
9; CHECK-NEXT:    vminnm.f32 s0, s2, s0
10; CHECK-NEXT:    vmov r0, s0
11; CHECK-NEXT:    eor r0, r0, #-2147483648
12; CHECK-NEXT:    mov pc, lr
13  %fneg.a = fneg nnan nsz float %a
14  %cmp.a = fcmp nnan nsz olt float %a, -8.0
15  %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
16  ret float %min.a
17}
18
19define half @select_fneg_a_or_8_cmp_olt_a_neg8_f16(half %a, half %b) #0 {
20; CHECK-LABEL: select_fneg_a_or_8_cmp_olt_a_neg8_f16:
21; CHECK:       @ %bb.0:
22; CHECK-NEXT:    vmov.f16 s0, #-8.000000e+00
23; CHECK-NEXT:    vmov.f16 s2, r0
24; CHECK-NEXT:    vminnm.f16 s0, s2, s0
25; CHECK-NEXT:    vneg.f16 s0, s0
26; CHECK-NEXT:    vmov r0, s0
27; CHECK-NEXT:    mov pc, lr
28  %fneg.a = fneg nnan nsz half %a
29  %cmp.a = fcmp nnan nsz olt half %a, -8.0
30  %min.a = select nnan nsz i1 %cmp.a, half %fneg.a, half 8.0
31  ret half %min.a
32}
33
34define float @select_fneg_a_or_8_cmp_ogt_a_neg8_f32(float %a, float %b) #0 {
35; CHECK-LABEL: select_fneg_a_or_8_cmp_ogt_a_neg8_f32:
36; CHECK:       @ %bb.0:
37; CHECK-NEXT:    vmov.f32 s0, #-8.000000e+00
38; CHECK-NEXT:    vmov s2, r0
39; CHECK-NEXT:    vmaxnm.f32 s0, s2, s0
40; CHECK-NEXT:    vmov r0, s0
41; CHECK-NEXT:    eor r0, r0, #-2147483648
42; CHECK-NEXT:    mov pc, lr
43  %fneg.a = fneg nnan nsz float %a
44  %cmp.a = fcmp nnan nsz ogt float %a, -8.0
45  %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
46  ret float %min.a
47}
48
49define half @select_fneg_a_or_8_cmp_ogt_a_neg8_f16(half %a, half %b) #0 {
50; CHECK-LABEL: select_fneg_a_or_8_cmp_ogt_a_neg8_f16:
51; CHECK:       @ %bb.0:
52; CHECK-NEXT:    vmov.f16 s0, #-8.000000e+00
53; CHECK-NEXT:    vmov.f16 s2, r0
54; CHECK-NEXT:    vmaxnm.f16 s0, s2, s0
55; CHECK-NEXT:    vneg.f16 s0, s0
56; CHECK-NEXT:    vmov r0, s0
57; CHECK-NEXT:    mov pc, lr
58  %fneg.a = fneg nnan nsz half %a
59  %cmp.a = fcmp nnan nsz ogt half %a, -8.0
60  %min.a = select nnan nsz i1 %cmp.a, half %fneg.a, half 8.0
61  ret half %min.a
62}
63
64define float @select_fsub0_or_8_cmp_olt_fsub1_neg8_f32(float %a, float %b) #0 {
65; CHECK-LABEL: select_fsub0_or_8_cmp_olt_fsub1_neg8_f32:
66; CHECK:       @ %bb.0:
67; CHECK-NEXT:    vmov.f32 s0, #4.000000e+00
68; CHECK-NEXT:    vmov s2, r0
69; CHECK-NEXT:    vmov.f32 s4, #-8.000000e+00
70; CHECK-NEXT:    vsub.f32 s0, s0, s2
71; CHECK-NEXT:    vminnm.f32 s0, s0, s4
72; CHECK-NEXT:    vmov r0, s0
73; CHECK-NEXT:    eor r0, r0, #-2147483648
74; CHECK-NEXT:    mov pc, lr
75  %sub.0 = fsub nnan nsz float 4.0, %a
76  %sub.1 = fsub nnan nsz float %a, 4.0
77  %cmp.a = fcmp nnan nsz olt float %sub.0, -8.0
78  %min.a = select nnan nsz i1 %cmp.a, float %sub.1, float 8.0
79  ret float %min.a
80}
81
82define float @select_fsub0_or_neg8_cmp_olt_fsub1_8_f32(float %a, float %b) #0 {
83; CHECK-LABEL: select_fsub0_or_neg8_cmp_olt_fsub1_8_f32:
84; CHECK:       @ %bb.0:
85; CHECK-NEXT:    vmov.f32 s0, #4.000000e+00
86; CHECK-NEXT:    vmov s2, r0
87; CHECK-NEXT:    vmov.f32 s4, #8.000000e+00
88; CHECK-NEXT:    vsub.f32 s0, s0, s2
89; CHECK-NEXT:    vminnm.f32 s0, s0, s4
90; CHECK-NEXT:    vmov r0, s0
91; CHECK-NEXT:    eor r0, r0, #-2147483648
92; CHECK-NEXT:    mov pc, lr
93  %sub.0 = fsub nnan nsz float 4.0, %a
94  %sub.1 = fsub nnan nsz float %a, 4.0
95  %cmp.a = fcmp nnan nsz olt float %sub.0, 8.0
96  %min.a = select nnan nsz i1 %cmp.a, float %sub.1, float -8.0
97  ret float %min.a
98}
99
100define float @select_mul4_or_neg8_cmp_olt_mulneg4_8_f32(float %a, float %b) #0 {
101; CHECK-LABEL: select_mul4_or_neg8_cmp_olt_mulneg4_8_f32:
102; CHECK:       @ %bb.0:
103; CHECK-NEXT:    vmov.f32 s0, #-4.000000e+00
104; CHECK-NEXT:    vmov s2, r0
105; CHECK-NEXT:    vmov.f32 s4, #8.000000e+00
106; CHECK-NEXT:    vmul.f32 s0, s2, s0
107; CHECK-NEXT:    vminnm.f32 s0, s0, s4
108; CHECK-NEXT:    vmov r0, s0
109; CHECK-NEXT:    eor r0, r0, #-2147483648
110; CHECK-NEXT:    mov pc, lr
111  %mul.0 = fmul nnan nsz float %a, 4.0
112  %mul.1 = fmul nnan nsz float %a, -4.0
113  %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0
114  %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0
115  ret float %min.a
116}
117
118define float @select_mul4_or_8_cmp_olt_mulneg4_neg8_f32(float %a, float %b) #0 {
119; CHECK-LABEL: select_mul4_or_8_cmp_olt_mulneg4_neg8_f32:
120; CHECK:       @ %bb.0:
121; CHECK-NEXT:    vmov.f32 s0, #-4.000000e+00
122; CHECK-NEXT:    vmov s2, r0
123; CHECK-NEXT:    vmov.f32 s4, #-8.000000e+00
124; CHECK-NEXT:    vmul.f32 s0, s2, s0
125; CHECK-NEXT:    vminnm.f32 s0, s0, s4
126; CHECK-NEXT:    vmov r0, s0
127; CHECK-NEXT:    eor r0, r0, #-2147483648
128; CHECK-NEXT:    mov pc, lr
129  %mul.0 = fmul nnan nsz float %a, 4.0
130  %mul.1 = fmul nnan nsz float %a, -4.0
131  %cmp.a = fcmp nnan nsz olt float %mul.1, -8.0
132  %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float 8.0
133  ret float %min.a
134}
135
136define float @select_mul4_or_8_cmp_olt_mulneg4_8_f32(float %a, float %b) #0 {
137; CHECK-LABEL: select_mul4_or_8_cmp_olt_mulneg4_8_f32:
138; CHECK:       @ %bb.0:
139; CHECK-NEXT:    vmov.f32 s0, #-4.000000e+00
140; CHECK-NEXT:    vmov s2, r0
141; CHECK-NEXT:    vmov.f32 s6, #8.000000e+00
142; CHECK-NEXT:    vmov.f32 s4, #4.000000e+00
143; CHECK-NEXT:    vmul.f32 s0, s2, s0
144; CHECK-NEXT:    vmul.f32 s2, s2, s4
145; CHECK-NEXT:    vcmp.f32 s6, s0
146; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
147; CHECK-NEXT:    vselgt.f32 s0, s2, s6
148; CHECK-NEXT:    vmov r0, s0
149; CHECK-NEXT:    mov pc, lr
150  %mul.0 = fmul nnan nsz float %a, 4.0
151  %mul.1 = fmul nnan nsz float %a, -4.0
152  %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0
153  %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float 8.0
154  ret float %min.a
155}
156
157define float @select_mul4_or_neg8_cmp_olt_mulneg4_neg8_f32(float %a, float %b) #0 {
158; CHECK-LABEL: select_mul4_or_neg8_cmp_olt_mulneg4_neg8_f32:
159; CHECK:       @ %bb.0:
160; CHECK-NEXT:    vmov.f32 s0, #-4.000000e+00
161; CHECK-NEXT:    vmov s2, r0
162; CHECK-NEXT:    vmov.f32 s6, #-8.000000e+00
163; CHECK-NEXT:    vmov.f32 s4, #4.000000e+00
164; CHECK-NEXT:    vmul.f32 s0, s2, s0
165; CHECK-NEXT:    vmul.f32 s2, s2, s4
166; CHECK-NEXT:    vcmp.f32 s6, s0
167; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
168; CHECK-NEXT:    vselgt.f32 s0, s2, s6
169; CHECK-NEXT:    vmov r0, s0
170; CHECK-NEXT:    mov pc, lr
171  %mul.0 = fmul nnan nsz float %a, 4.0
172  %mul.1 = fmul nnan nsz float %a, -4.0
173  %cmp.a = fcmp nnan nsz olt float %mul.1, -8.0
174  %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0
175  ret float %min.a
176}
177
178define float @select_mulneg4_or_neg8_cmp_olt_mul4_8_f32(float %a, float %b) #0 {
179; CHECK-LABEL: select_mulneg4_or_neg8_cmp_olt_mul4_8_f32:
180; CHECK:       @ %bb.0:
181; CHECK-NEXT:    vmov.f32 s0, #4.000000e+00
182; CHECK-NEXT:    vmov s2, r0
183; CHECK-NEXT:    vmov.f32 s4, #8.000000e+00
184; CHECK-NEXT:    vmul.f32 s0, s2, s0
185; CHECK-NEXT:    vminnm.f32 s0, s0, s4
186; CHECK-NEXT:    vmov r0, s0
187; CHECK-NEXT:    eor r0, r0, #-2147483648
188; CHECK-NEXT:    mov pc, lr
189  %mul.0 = fmul nnan nsz float %a, -4.0
190  %mul.1 = fmul nnan nsz float %a, 4.0
191  %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0
192  %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0
193  ret float %min.a
194}
195
196; FIXME: Should be unnecessary
197attributes #0 = { "no-signed-zeros-fp-math"="true" }
198