1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=armv7-unknown-eabi %s -o - | FileCheck %s 3 4define i8 @ucmp_8_8(i8 zeroext %x, i8 zeroext %y) nounwind { 5; CHECK-LABEL: ucmp_8_8: 6; CHECK: @ %bb.0: 7; CHECK-NEXT: cmp r0, r1 8; CHECK-NEXT: mov r0, #0 9; CHECK-NEXT: mov r2, #0 10; CHECK-NEXT: movwlo r0, #1 11; CHECK-NEXT: movwhi r2, #1 12; CHECK-NEXT: sub r0, r2, r0 13; CHECK-NEXT: bx lr 14 %1 = call i8 @llvm.ucmp(i8 %x, i8 %y) 15 ret i8 %1 16} 17 18define i8 @ucmp_8_16(i16 zeroext %x, i16 zeroext %y) nounwind { 19; CHECK-LABEL: ucmp_8_16: 20; CHECK: @ %bb.0: 21; CHECK-NEXT: cmp r0, r1 22; CHECK-NEXT: mov r0, #0 23; CHECK-NEXT: mov r2, #0 24; CHECK-NEXT: movwlo r0, #1 25; CHECK-NEXT: movwhi r2, #1 26; CHECK-NEXT: sub r0, r2, r0 27; CHECK-NEXT: bx lr 28 %1 = call i8 @llvm.ucmp(i16 %x, i16 %y) 29 ret i8 %1 30} 31 32define i8 @ucmp_8_32(i32 %x, i32 %y) nounwind { 33; CHECK-LABEL: ucmp_8_32: 34; CHECK: @ %bb.0: 35; CHECK-NEXT: cmp r0, r1 36; CHECK-NEXT: mov r0, #0 37; CHECK-NEXT: mov r2, #0 38; CHECK-NEXT: movwlo r0, #1 39; CHECK-NEXT: movwhi r2, #1 40; CHECK-NEXT: sub r0, r2, r0 41; CHECK-NEXT: bx lr 42 %1 = call i8 @llvm.ucmp(i32 %x, i32 %y) 43 ret i8 %1 44} 45 46define i8 @ucmp_8_64(i64 %x, i64 %y) nounwind { 47; CHECK-LABEL: ucmp_8_64: 48; CHECK: @ %bb.0: 49; CHECK-NEXT: .save {r11, lr} 50; CHECK-NEXT: push {r11, lr} 51; CHECK-NEXT: subs lr, r0, r2 52; CHECK-NEXT: mov r12, #0 53; CHECK-NEXT: sbcs lr, r1, r3 54; CHECK-NEXT: mov lr, #0 55; CHECK-NEXT: movwlo lr, #1 56; CHECK-NEXT: subs r0, r2, r0 57; CHECK-NEXT: sbcs r0, r3, r1 58; CHECK-NEXT: movwlo r12, #1 59; CHECK-NEXT: sub r0, r12, lr 60; CHECK-NEXT: pop {r11, pc} 61 %1 = call i8 @llvm.ucmp(i64 %x, i64 %y) 62 ret i8 %1 63} 64 65define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind { 66; CHECK-LABEL: ucmp_8_128: 67; CHECK: @ %bb.0: 68; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr} 69; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr} 70; CHECK-NEXT: ldr r4, [sp, #24] 71; CHECK-NEXT: mov r5, #0 72; CHECK-NEXT: ldr r6, [sp, #28] 73; CHECK-NEXT: subs r7, r0, r4 74; CHECK-NEXT: ldr r12, [sp, #32] 75; CHECK-NEXT: sbcs r7, r1, r6 76; CHECK-NEXT: ldr lr, [sp, #36] 77; CHECK-NEXT: sbcs r7, r2, r12 78; CHECK-NEXT: sbcs r7, r3, lr 79; CHECK-NEXT: mov r7, #0 80; CHECK-NEXT: movwlo r7, #1 81; CHECK-NEXT: subs r0, r4, r0 82; CHECK-NEXT: sbcs r0, r6, r1 83; CHECK-NEXT: sbcs r0, r12, r2 84; CHECK-NEXT: sbcs r0, lr, r3 85; CHECK-NEXT: movwlo r5, #1 86; CHECK-NEXT: sub r0, r5, r7 87; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc} 88 %1 = call i8 @llvm.ucmp(i128 %x, i128 %y) 89 ret i8 %1 90} 91 92define i32 @ucmp_32_32(i32 %x, i32 %y) nounwind { 93; CHECK-LABEL: ucmp_32_32: 94; CHECK: @ %bb.0: 95; CHECK-NEXT: cmp r0, r1 96; CHECK-NEXT: mov r0, #0 97; CHECK-NEXT: mov r2, #0 98; CHECK-NEXT: movwlo r0, #1 99; CHECK-NEXT: movwhi r2, #1 100; CHECK-NEXT: sub r0, r2, r0 101; CHECK-NEXT: bx lr 102 %1 = call i32 @llvm.ucmp(i32 %x, i32 %y) 103 ret i32 %1 104} 105 106define i32 @ucmp_32_64(i64 %x, i64 %y) nounwind { 107; CHECK-LABEL: ucmp_32_64: 108; CHECK: @ %bb.0: 109; CHECK-NEXT: .save {r11, lr} 110; CHECK-NEXT: push {r11, lr} 111; CHECK-NEXT: subs lr, r0, r2 112; CHECK-NEXT: mov r12, #0 113; CHECK-NEXT: sbcs lr, r1, r3 114; CHECK-NEXT: mov lr, #0 115; CHECK-NEXT: movwlo lr, #1 116; CHECK-NEXT: subs r0, r2, r0 117; CHECK-NEXT: sbcs r0, r3, r1 118; CHECK-NEXT: movwlo r12, #1 119; CHECK-NEXT: sub r0, r12, lr 120; CHECK-NEXT: pop {r11, pc} 121 %1 = call i32 @llvm.ucmp(i64 %x, i64 %y) 122 ret i32 %1 123} 124 125define i64 @ucmp_64_64(i64 %x, i64 %y) nounwind { 126; CHECK-LABEL: ucmp_64_64: 127; CHECK: @ %bb.0: 128; CHECK-NEXT: .save {r11, lr} 129; CHECK-NEXT: push {r11, lr} 130; CHECK-NEXT: subs lr, r0, r2 131; CHECK-NEXT: mov r12, #0 132; CHECK-NEXT: sbcs lr, r1, r3 133; CHECK-NEXT: mov lr, #0 134; CHECK-NEXT: movwlo lr, #1 135; CHECK-NEXT: subs r0, r2, r0 136; CHECK-NEXT: sbcs r0, r3, r1 137; CHECK-NEXT: movwlo r12, #1 138; CHECK-NEXT: sub r0, r12, lr 139; CHECK-NEXT: asr r1, r0, #31 140; CHECK-NEXT: pop {r11, pc} 141 %1 = call i64 @llvm.ucmp(i64 %x, i64 %y) 142 ret i64 %1 143} 144