1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1 3; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP 4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP 5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM 6 7declare i4 @llvm.uadd.sat.i4(i4, i4) 8declare i8 @llvm.uadd.sat.i8(i8, i8) 9declare i16 @llvm.uadd.sat.i16(i16, i16) 10declare i32 @llvm.uadd.sat.i32(i32, i32) 11declare i64 @llvm.uadd.sat.i64(i64, i64) 12 13define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind { 14; CHECK-T1-LABEL: func32: 15; CHECK-T1: @ %bb.0: 16; CHECK-T1-NEXT: muls r1, r2, r1 17; CHECK-T1-NEXT: adds r0, r0, r1 18; CHECK-T1-NEXT: blo .LBB0_2 19; CHECK-T1-NEXT: @ %bb.1: 20; CHECK-T1-NEXT: movs r0, #0 21; CHECK-T1-NEXT: mvns r0, r0 22; CHECK-T1-NEXT: .LBB0_2: 23; CHECK-T1-NEXT: bx lr 24; 25; CHECK-T2-LABEL: func32: 26; CHECK-T2: @ %bb.0: 27; CHECK-T2-NEXT: muls r1, r2, r1 28; CHECK-T2-NEXT: adds r0, r0, r1 29; CHECK-T2-NEXT: it hs 30; CHECK-T2-NEXT: movhs.w r0, #-1 31; CHECK-T2-NEXT: bx lr 32; 33; CHECK-ARM-LABEL: func32: 34; CHECK-ARM: @ %bb.0: 35; CHECK-ARM-NEXT: mul r1, r1, r2 36; CHECK-ARM-NEXT: adds r0, r0, r1 37; CHECK-ARM-NEXT: mvnhs r0, #0 38; CHECK-ARM-NEXT: bx lr 39 %a = mul i32 %y, %z 40 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a) 41 ret i32 %tmp 42} 43 44define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { 45; CHECK-T1-LABEL: func64: 46; CHECK-T1: @ %bb.0: 47; CHECK-T1-NEXT: .save {r4, lr} 48; CHECK-T1-NEXT: push {r4, lr} 49; CHECK-T1-NEXT: movs r4, #0 50; CHECK-T1-NEXT: ldr r2, [sp, #12] 51; CHECK-T1-NEXT: ldr r3, [sp, #8] 52; CHECK-T1-NEXT: adds r3, r0, r3 53; CHECK-T1-NEXT: adcs r2, r1 54; CHECK-T1-NEXT: mov r0, r4 55; CHECK-T1-NEXT: adcs r0, r4 56; CHECK-T1-NEXT: mvns r1, r4 57; CHECK-T1-NEXT: cmp r0, #0 58; CHECK-T1-NEXT: mov r0, r1 59; CHECK-T1-NEXT: beq .LBB1_3 60; CHECK-T1-NEXT: @ %bb.1: 61; CHECK-T1-NEXT: beq .LBB1_4 62; CHECK-T1-NEXT: .LBB1_2: 63; CHECK-T1-NEXT: pop {r4, pc} 64; CHECK-T1-NEXT: .LBB1_3: 65; CHECK-T1-NEXT: mov r0, r3 66; CHECK-T1-NEXT: bne .LBB1_2 67; CHECK-T1-NEXT: .LBB1_4: 68; CHECK-T1-NEXT: mov r1, r2 69; CHECK-T1-NEXT: pop {r4, pc} 70; 71; CHECK-T2-LABEL: func64: 72; CHECK-T2: @ %bb.0: 73; CHECK-T2-NEXT: ldrd r2, r3, [sp] 74; CHECK-T2-NEXT: mov.w r12, #0 75; CHECK-T2-NEXT: adds r0, r0, r2 76; CHECK-T2-NEXT: adcs r1, r3 77; CHECK-T2-NEXT: adcs r2, r12, #0 78; CHECK-T2-NEXT: itt ne 79; CHECK-T2-NEXT: movne.w r0, #-1 80; CHECK-T2-NEXT: movne.w r1, #-1 81; CHECK-T2-NEXT: bx lr 82; 83; CHECK-ARM-LABEL: func64: 84; CHECK-ARM: @ %bb.0: 85; CHECK-ARM-NEXT: ldr r2, [sp] 86; CHECK-ARM-NEXT: mov r12, #0 87; CHECK-ARM-NEXT: ldr r3, [sp, #4] 88; CHECK-ARM-NEXT: adds r0, r0, r2 89; CHECK-ARM-NEXT: adcs r1, r1, r3 90; CHECK-ARM-NEXT: adcs r2, r12, #0 91; CHECK-ARM-NEXT: mvnne r0, #0 92; CHECK-ARM-NEXT: mvnne r1, #0 93; CHECK-ARM-NEXT: bx lr 94 %a = mul i64 %y, %z 95 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z) 96 ret i64 %tmp 97} 98 99define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind { 100; CHECK-T1-LABEL: func16: 101; CHECK-T1: @ %bb.0: 102; CHECK-T1-NEXT: muls r1, r2, r1 103; CHECK-T1-NEXT: uxth r1, r1 104; CHECK-T1-NEXT: adds r0, r0, r1 105; CHECK-T1-NEXT: ldr r1, .LCPI2_0 106; CHECK-T1-NEXT: cmp r0, r1 107; CHECK-T1-NEXT: blo .LBB2_2 108; CHECK-T1-NEXT: @ %bb.1: 109; CHECK-T1-NEXT: mov r0, r1 110; CHECK-T1-NEXT: .LBB2_2: 111; CHECK-T1-NEXT: bx lr 112; CHECK-T1-NEXT: .p2align 2 113; CHECK-T1-NEXT: @ %bb.3: 114; CHECK-T1-NEXT: .LCPI2_0: 115; CHECK-T1-NEXT: .long 65535 @ 0xffff 116; 117; CHECK-T2NODSP-LABEL: func16: 118; CHECK-T2NODSP: @ %bb.0: 119; CHECK-T2NODSP-NEXT: muls r1, r2, r1 120; CHECK-T2NODSP-NEXT: uxth r1, r1 121; CHECK-T2NODSP-NEXT: add r1, r0 122; CHECK-T2NODSP-NEXT: movw r0, #65535 123; CHECK-T2NODSP-NEXT: cmp r1, r0 124; CHECK-T2NODSP-NEXT: it lo 125; CHECK-T2NODSP-NEXT: movlo r0, r1 126; CHECK-T2NODSP-NEXT: bx lr 127; 128; CHECK-T2DSP-LABEL: func16: 129; CHECK-T2DSP: @ %bb.0: 130; CHECK-T2DSP-NEXT: muls r1, r2, r1 131; CHECK-T2DSP-NEXT: uqadd16 r0, r0, r1 132; CHECK-T2DSP-NEXT: uxth r0, r0 133; CHECK-T2DSP-NEXT: bx lr 134; 135; CHECK-ARM-LABEL: func16: 136; CHECK-ARM: @ %bb.0: 137; CHECK-ARM-NEXT: mul r1, r1, r2 138; CHECK-ARM-NEXT: uqadd16 r0, r0, r1 139; CHECK-ARM-NEXT: uxth r0, r0 140; CHECK-ARM-NEXT: bx lr 141 %a = mul i16 %y, %z 142 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a) 143 ret i16 %tmp 144} 145 146define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind { 147; CHECK-T1-LABEL: func8: 148; CHECK-T1: @ %bb.0: 149; CHECK-T1-NEXT: muls r1, r2, r1 150; CHECK-T1-NEXT: uxtb r1, r1 151; CHECK-T1-NEXT: adds r0, r0, r1 152; CHECK-T1-NEXT: cmp r0, #255 153; CHECK-T1-NEXT: blo .LBB3_2 154; CHECK-T1-NEXT: @ %bb.1: 155; CHECK-T1-NEXT: movs r0, #255 156; CHECK-T1-NEXT: .LBB3_2: 157; CHECK-T1-NEXT: bx lr 158; 159; CHECK-T2NODSP-LABEL: func8: 160; CHECK-T2NODSP: @ %bb.0: 161; CHECK-T2NODSP-NEXT: muls r1, r2, r1 162; CHECK-T2NODSP-NEXT: uxtb r1, r1 163; CHECK-T2NODSP-NEXT: add r0, r1 164; CHECK-T2NODSP-NEXT: cmp r0, #255 165; CHECK-T2NODSP-NEXT: it hs 166; CHECK-T2NODSP-NEXT: movhs r0, #255 167; CHECK-T2NODSP-NEXT: bx lr 168; 169; CHECK-T2DSP-LABEL: func8: 170; CHECK-T2DSP: @ %bb.0: 171; CHECK-T2DSP-NEXT: muls r1, r2, r1 172; CHECK-T2DSP-NEXT: uqadd8 r0, r0, r1 173; CHECK-T2DSP-NEXT: uxtb r0, r0 174; CHECK-T2DSP-NEXT: bx lr 175; 176; CHECK-ARM-LABEL: func8: 177; CHECK-ARM: @ %bb.0: 178; CHECK-ARM-NEXT: smulbb r1, r1, r2 179; CHECK-ARM-NEXT: uqadd8 r0, r0, r1 180; CHECK-ARM-NEXT: uxtb r0, r0 181; CHECK-ARM-NEXT: bx lr 182 %a = mul i8 %y, %z 183 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a) 184 ret i8 %tmp 185} 186 187define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind { 188; CHECK-T1-LABEL: func4: 189; CHECK-T1: @ %bb.0: 190; CHECK-T1-NEXT: muls r1, r2, r1 191; CHECK-T1-NEXT: movs r2, #15 192; CHECK-T1-NEXT: ands r1, r2 193; CHECK-T1-NEXT: adds r0, r0, r1 194; CHECK-T1-NEXT: cmp r0, #15 195; CHECK-T1-NEXT: blo .LBB4_2 196; CHECK-T1-NEXT: @ %bb.1: 197; CHECK-T1-NEXT: mov r0, r2 198; CHECK-T1-NEXT: .LBB4_2: 199; CHECK-T1-NEXT: bx lr 200; 201; CHECK-T2-LABEL: func4: 202; CHECK-T2: @ %bb.0: 203; CHECK-T2-NEXT: muls r1, r2, r1 204; CHECK-T2-NEXT: and r1, r1, #15 205; CHECK-T2-NEXT: add r0, r1 206; CHECK-T2-NEXT: cmp r0, #15 207; CHECK-T2-NEXT: it hs 208; CHECK-T2-NEXT: movhs r0, #15 209; CHECK-T2-NEXT: bx lr 210; 211; CHECK-ARM-LABEL: func4: 212; CHECK-ARM: @ %bb.0: 213; CHECK-ARM-NEXT: smulbb r1, r1, r2 214; CHECK-ARM-NEXT: and r1, r1, #15 215; CHECK-ARM-NEXT: add r0, r0, r1 216; CHECK-ARM-NEXT: cmp r0, #15 217; CHECK-ARM-NEXT: movhs r0, #15 218; CHECK-ARM-NEXT: bx lr 219 %a = mul i4 %y, %z 220 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a) 221 ret i4 %tmp 222} 223