1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1 3; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP 4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP 5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM 6 7declare i4 @llvm.uadd.sat.i4(i4, i4) 8declare i8 @llvm.uadd.sat.i8(i8, i8) 9declare i16 @llvm.uadd.sat.i16(i16, i16) 10declare i32 @llvm.uadd.sat.i32(i32, i32) 11declare i64 @llvm.uadd.sat.i64(i64, i64) 12 13define i32 @func(i32 %x, i32 %y) nounwind { 14; CHECK-T1-LABEL: func: 15; CHECK-T1: @ %bb.0: 16; CHECK-T1-NEXT: adds r0, r0, r1 17; CHECK-T1-NEXT: blo .LBB0_2 18; CHECK-T1-NEXT: @ %bb.1: 19; CHECK-T1-NEXT: movs r0, #0 20; CHECK-T1-NEXT: mvns r0, r0 21; CHECK-T1-NEXT: .LBB0_2: 22; CHECK-T1-NEXT: bx lr 23; 24; CHECK-T2-LABEL: func: 25; CHECK-T2: @ %bb.0: 26; CHECK-T2-NEXT: adds r0, r0, r1 27; CHECK-T2-NEXT: it hs 28; CHECK-T2-NEXT: movhs.w r0, #-1 29; CHECK-T2-NEXT: bx lr 30; 31; CHECK-ARM-LABEL: func: 32; CHECK-ARM: @ %bb.0: 33; CHECK-ARM-NEXT: adds r0, r0, r1 34; CHECK-ARM-NEXT: mvnhs r0, #0 35; CHECK-ARM-NEXT: bx lr 36 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y) 37 ret i32 %tmp 38} 39 40define i64 @func2(i64 %x, i64 %y) nounwind { 41; CHECK-T1-LABEL: func2: 42; CHECK-T1: @ %bb.0: 43; CHECK-T1-NEXT: .save {r4, r5, r7, lr} 44; CHECK-T1-NEXT: push {r4, r5, r7, lr} 45; CHECK-T1-NEXT: movs r5, #0 46; CHECK-T1-NEXT: adds r4, r0, r2 47; CHECK-T1-NEXT: adcs r1, r3 48; CHECK-T1-NEXT: mov r0, r5 49; CHECK-T1-NEXT: adcs r0, r5 50; CHECK-T1-NEXT: mvns r2, r5 51; CHECK-T1-NEXT: cmp r0, #0 52; CHECK-T1-NEXT: mov r0, r2 53; CHECK-T1-NEXT: beq .LBB1_3 54; CHECK-T1-NEXT: @ %bb.1: 55; CHECK-T1-NEXT: beq .LBB1_4 56; CHECK-T1-NEXT: .LBB1_2: 57; CHECK-T1-NEXT: mov r1, r2 58; CHECK-T1-NEXT: pop {r4, r5, r7, pc} 59; CHECK-T1-NEXT: .LBB1_3: 60; CHECK-T1-NEXT: mov r0, r4 61; CHECK-T1-NEXT: bne .LBB1_2 62; CHECK-T1-NEXT: .LBB1_4: 63; CHECK-T1-NEXT: mov r2, r1 64; CHECK-T1-NEXT: mov r1, r2 65; CHECK-T1-NEXT: pop {r4, r5, r7, pc} 66; 67; CHECK-T2-LABEL: func2: 68; CHECK-T2: @ %bb.0: 69; CHECK-T2-NEXT: adds r0, r0, r2 70; CHECK-T2-NEXT: mov.w r12, #0 71; CHECK-T2-NEXT: adcs r1, r3 72; CHECK-T2-NEXT: adcs r2, r12, #0 73; CHECK-T2-NEXT: itt ne 74; CHECK-T2-NEXT: movne.w r0, #-1 75; CHECK-T2-NEXT: movne.w r1, #-1 76; CHECK-T2-NEXT: bx lr 77; 78; CHECK-ARM-LABEL: func2: 79; CHECK-ARM: @ %bb.0: 80; CHECK-ARM-NEXT: adds r0, r0, r2 81; CHECK-ARM-NEXT: mov r12, #0 82; CHECK-ARM-NEXT: adcs r1, r1, r3 83; CHECK-ARM-NEXT: adcs r2, r12, #0 84; CHECK-ARM-NEXT: mvnne r0, #0 85; CHECK-ARM-NEXT: mvnne r1, #0 86; CHECK-ARM-NEXT: bx lr 87 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y) 88 ret i64 %tmp 89} 90 91define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind { 92; CHECK-T1-LABEL: func16: 93; CHECK-T1: @ %bb.0: 94; CHECK-T1-NEXT: adds r0, r0, r1 95; CHECK-T1-NEXT: ldr r1, .LCPI2_0 96; CHECK-T1-NEXT: cmp r0, r1 97; CHECK-T1-NEXT: blo .LBB2_2 98; CHECK-T1-NEXT: @ %bb.1: 99; CHECK-T1-NEXT: mov r0, r1 100; CHECK-T1-NEXT: .LBB2_2: 101; CHECK-T1-NEXT: bx lr 102; CHECK-T1-NEXT: .p2align 2 103; CHECK-T1-NEXT: @ %bb.3: 104; CHECK-T1-NEXT: .LCPI2_0: 105; CHECK-T1-NEXT: .long 65535 @ 0xffff 106; 107; CHECK-T2NODSP-LABEL: func16: 108; CHECK-T2NODSP: @ %bb.0: 109; CHECK-T2NODSP-NEXT: add r1, r0 110; CHECK-T2NODSP-NEXT: movw r0, #65535 111; CHECK-T2NODSP-NEXT: cmp r1, r0 112; CHECK-T2NODSP-NEXT: it lo 113; CHECK-T2NODSP-NEXT: movlo r0, r1 114; CHECK-T2NODSP-NEXT: bx lr 115; 116; CHECK-T2DSP-LABEL: func16: 117; CHECK-T2DSP: @ %bb.0: 118; CHECK-T2DSP-NEXT: uqadd16 r0, r0, r1 119; CHECK-T2DSP-NEXT: uxth r0, r0 120; CHECK-T2DSP-NEXT: bx lr 121; 122; CHECK-ARM-LABEL: func16: 123; CHECK-ARM: @ %bb.0: 124; CHECK-ARM-NEXT: uqadd16 r0, r0, r1 125; CHECK-ARM-NEXT: uxth r0, r0 126; CHECK-ARM-NEXT: bx lr 127 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y) 128 ret i16 %tmp 129} 130 131define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind { 132; CHECK-T1-LABEL: func8: 133; CHECK-T1: @ %bb.0: 134; CHECK-T1-NEXT: adds r0, r0, r1 135; CHECK-T1-NEXT: cmp r0, #255 136; CHECK-T1-NEXT: blo .LBB3_2 137; CHECK-T1-NEXT: @ %bb.1: 138; CHECK-T1-NEXT: movs r0, #255 139; CHECK-T1-NEXT: .LBB3_2: 140; CHECK-T1-NEXT: bx lr 141; 142; CHECK-T2NODSP-LABEL: func8: 143; CHECK-T2NODSP: @ %bb.0: 144; CHECK-T2NODSP-NEXT: add r0, r1 145; CHECK-T2NODSP-NEXT: cmp r0, #255 146; CHECK-T2NODSP-NEXT: it hs 147; CHECK-T2NODSP-NEXT: movhs r0, #255 148; CHECK-T2NODSP-NEXT: bx lr 149; 150; CHECK-T2DSP-LABEL: func8: 151; CHECK-T2DSP: @ %bb.0: 152; CHECK-T2DSP-NEXT: uqadd8 r0, r0, r1 153; CHECK-T2DSP-NEXT: uxtb r0, r0 154; CHECK-T2DSP-NEXT: bx lr 155; 156; CHECK-ARM-LABEL: func8: 157; CHECK-ARM: @ %bb.0: 158; CHECK-ARM-NEXT: uqadd8 r0, r0, r1 159; CHECK-ARM-NEXT: uxtb r0, r0 160; CHECK-ARM-NEXT: bx lr 161 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y) 162 ret i8 %tmp 163} 164 165define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind { 166; CHECK-T1-LABEL: func3: 167; CHECK-T1: @ %bb.0: 168; CHECK-T1-NEXT: adds r0, r0, r1 169; CHECK-T1-NEXT: cmp r0, #15 170; CHECK-T1-NEXT: blo .LBB4_2 171; CHECK-T1-NEXT: @ %bb.1: 172; CHECK-T1-NEXT: movs r0, #15 173; CHECK-T1-NEXT: .LBB4_2: 174; CHECK-T1-NEXT: bx lr 175; 176; CHECK-T2-LABEL: func3: 177; CHECK-T2: @ %bb.0: 178; CHECK-T2-NEXT: add r0, r1 179; CHECK-T2-NEXT: cmp r0, #15 180; CHECK-T2-NEXT: it hs 181; CHECK-T2-NEXT: movhs r0, #15 182; CHECK-T2-NEXT: bx lr 183; 184; CHECK-ARM-LABEL: func3: 185; CHECK-ARM: @ %bb.0: 186; CHECK-ARM-NEXT: add r0, r0, r1 187; CHECK-ARM-NEXT: cmp r0, #15 188; CHECK-ARM-NEXT: movhs r0, #15 189; CHECK-ARM-NEXT: bx lr 190 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y) 191 ret i4 %tmp 192} 193