1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=CHECK-ARM 3; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ 4; RUN: | FileCheck %s --check-prefix=CHECK-THUMB2 5 6;; Check how immediates are handled in add/sub. 7 8define i32 @sub0(i32 %0) { 9; CHECK-ARM-LABEL: sub0: 10; CHECK-ARM: @ %bb.0: 11; CHECK-ARM-NEXT: sub r0, r0, #23 12; CHECK-ARM-NEXT: mov pc, lr 13; 14; CHECK-THUMB2-LABEL: sub0: 15; CHECK-THUMB2: @ %bb.0: 16; CHECK-THUMB2-NEXT: subs r0, #23 17; CHECK-THUMB2-NEXT: bx lr 18 %2 = sub i32 %0, 23 19 ret i32 %2 20} 21 22define i32 @sub1(i32 %0) { 23; CHECK-ARM-LABEL: sub1: 24; CHECK-ARM: @ %bb.0: 25; CHECK-ARM-NEXT: ldr r1, .LCPI1_0 26; CHECK-ARM-NEXT: add r0, r0, r1 27; CHECK-ARM-NEXT: mov pc, lr 28; CHECK-ARM-NEXT: .p2align 2 29; CHECK-ARM-NEXT: @ %bb.1: 30; CHECK-ARM-NEXT: .LCPI1_0: 31; CHECK-ARM-NEXT: .long 4294836225 @ 0xfffe0001 32; 33; CHECK-THUMB2-LABEL: sub1: 34; CHECK-THUMB2: @ %bb.0: 35; CHECK-THUMB2-NEXT: movs r1, #1 36; CHECK-THUMB2-NEXT: movt r1, #65534 37; CHECK-THUMB2-NEXT: add r0, r1 38; CHECK-THUMB2-NEXT: bx lr 39 %2 = sub i32 %0, 131071 40 ret i32 %2 41} 42 43define i32 @sub2(i32 %0) { 44; CHECK-ARM-LABEL: sub2: 45; CHECK-ARM: @ %bb.0: 46; CHECK-ARM-NEXT: sub r0, r0, #35 47; CHECK-ARM-NEXT: sub r0, r0, #8960 48; CHECK-ARM-NEXT: mov pc, lr 49; 50; CHECK-THUMB2-LABEL: sub2: 51; CHECK-THUMB2: @ %bb.0: 52; CHECK-THUMB2-NEXT: movw r1, #8995 53; CHECK-THUMB2-NEXT: subs r0, r0, r1 54; CHECK-THUMB2-NEXT: bx lr 55 %2 = sub i32 %0, 8995 56 ret i32 %2 57} 58 59define i32 @sub3(i32 %0) { 60; CHECK-ARM-LABEL: sub3: 61; CHECK-ARM: @ %bb.0: 62; CHECK-ARM-NEXT: ldr r1, .LCPI3_0 63; CHECK-ARM-NEXT: add r0, r0, r1 64; CHECK-ARM-NEXT: mov pc, lr 65; CHECK-ARM-NEXT: .p2align 2 66; CHECK-ARM-NEXT: @ %bb.1: 67; CHECK-ARM-NEXT: .LCPI3_0: 68; CHECK-ARM-NEXT: .long 4292870571 @ 0xffe001ab 69; 70; CHECK-THUMB2-LABEL: sub3: 71; CHECK-THUMB2: @ %bb.0: 72; CHECK-THUMB2-NEXT: movw r1, #427 73; CHECK-THUMB2-NEXT: movt r1, #65504 74; CHECK-THUMB2-NEXT: add r0, r1 75; CHECK-THUMB2-NEXT: bx lr 76 %2 = sub i32 %0, 2096725 77 ret i32 %2 78} 79 80define i32 @sub4(i32 %0) { 81; CHECK-ARM-LABEL: sub4: 82; CHECK-ARM: @ %bb.0: 83; CHECK-ARM-NEXT: ldr r1, .LCPI4_0 84; CHECK-ARM-NEXT: add r0, r0, r1 85; CHECK-ARM-NEXT: mov pc, lr 86; CHECK-ARM-NEXT: .p2align 2 87; CHECK-ARM-NEXT: @ %bb.1: 88; CHECK-ARM-NEXT: .LCPI4_0: 89; CHECK-ARM-NEXT: .long 4286505147 @ 0xff7ee0bb 90; 91; CHECK-THUMB2-LABEL: sub4: 92; CHECK-THUMB2: @ %bb.0: 93; CHECK-THUMB2-NEXT: movw r1, #57531 94; CHECK-THUMB2-NEXT: movt r1, #65406 95; CHECK-THUMB2-NEXT: add r0, r1 96; CHECK-THUMB2-NEXT: bx lr 97 %2 = sub i32 %0, 8462149 98 ret i32 %2 99} 100define i32 @add0(i32 %0) { 101; CHECK-ARM-LABEL: add0: 102; CHECK-ARM: @ %bb.0: 103; CHECK-ARM-NEXT: add r0, r0, #23 104; CHECK-ARM-NEXT: mov pc, lr 105; 106; CHECK-THUMB2-LABEL: add0: 107; CHECK-THUMB2: @ %bb.0: 108; CHECK-THUMB2-NEXT: adds r0, #23 109; CHECK-THUMB2-NEXT: bx lr 110 %2 = add i32 %0, 23 111 ret i32 %2 112} 113 114define i32 @add1(i32 %0) { 115; CHECK-ARM-LABEL: add1: 116; CHECK-ARM: @ %bb.0: 117; CHECK-ARM-NEXT: ldr r1, .LCPI6_0 118; CHECK-ARM-NEXT: add r0, r0, r1 119; CHECK-ARM-NEXT: mov pc, lr 120; CHECK-ARM-NEXT: .p2align 2 121; CHECK-ARM-NEXT: @ %bb.1: 122; CHECK-ARM-NEXT: .LCPI6_0: 123; CHECK-ARM-NEXT: .long 131071 @ 0x1ffff 124; 125; CHECK-THUMB2-LABEL: add1: 126; CHECK-THUMB2: @ %bb.0: 127; CHECK-THUMB2-NEXT: movw r1, #65535 128; CHECK-THUMB2-NEXT: movt r1, #1 129; CHECK-THUMB2-NEXT: add r0, r1 130; CHECK-THUMB2-NEXT: bx lr 131 %2 = add i32 %0, 131071 132 ret i32 %2 133} 134 135define i32 @add2(i32 %0) { 136; CHECK-ARM-LABEL: add2: 137; CHECK-ARM: @ %bb.0: 138; CHECK-ARM-NEXT: add r0, r0, #8960 139; CHECK-ARM-NEXT: add r0, r0, #2293760 140; CHECK-ARM-NEXT: mov pc, lr 141; 142; CHECK-THUMB2-LABEL: add2: 143; CHECK-THUMB2: @ %bb.0: 144; CHECK-THUMB2-NEXT: add.w r0, r0, #2293760 145; CHECK-THUMB2-NEXT: add.w r0, r0, #8960 146; CHECK-THUMB2-NEXT: bx lr 147 %2 = add i32 %0, 2302720 148 ret i32 %2 149} 150 151define i32 @add3(i32 %0) { 152; CHECK-ARM-LABEL: add3: 153; CHECK-ARM: @ %bb.0: 154; CHECK-ARM-NEXT: ldr r1, .LCPI8_0 155; CHECK-ARM-NEXT: add r0, r0, r1 156; CHECK-ARM-NEXT: mov pc, lr 157; CHECK-ARM-NEXT: .p2align 2 158; CHECK-ARM-NEXT: @ %bb.1: 159; CHECK-ARM-NEXT: .LCPI8_0: 160; CHECK-ARM-NEXT: .long 2096725 @ 0x1ffe55 161; 162; CHECK-THUMB2-LABEL: add3: 163; CHECK-THUMB2: @ %bb.0: 164; CHECK-THUMB2-NEXT: movw r1, #65109 165; CHECK-THUMB2-NEXT: movt r1, #31 166; CHECK-THUMB2-NEXT: add r0, r1 167; CHECK-THUMB2-NEXT: bx lr 168 %2 = add i32 %0, 2096725 169 ret i32 %2 170} 171 172define i32 @add4(i32 %0) { 173; CHECK-ARM-LABEL: add4: 174; CHECK-ARM: @ %bb.0: 175; CHECK-ARM-NEXT: ldr r1, .LCPI9_0 176; CHECK-ARM-NEXT: add r0, r0, r1 177; CHECK-ARM-NEXT: mov pc, lr 178; CHECK-ARM-NEXT: .p2align 2 179; CHECK-ARM-NEXT: @ %bb.1: 180; CHECK-ARM-NEXT: .LCPI9_0: 181; CHECK-ARM-NEXT: .long 8462149 @ 0x811f45 182; 183; CHECK-THUMB2-LABEL: add4: 184; CHECK-THUMB2: @ %bb.0: 185; CHECK-THUMB2-NEXT: movw r1, #8005 186; CHECK-THUMB2-NEXT: movt r1, #129 187; CHECK-THUMB2-NEXT: add r0, r1 188; CHECK-THUMB2-NEXT: bx lr 189 %2 = add i32 %0, 8462149 190 ret i32 %2 191} 192 193define i32 @orr0(i32 %0) { 194; CHECK-ARM-LABEL: orr0: 195; CHECK-ARM: @ %bb.0: 196; CHECK-ARM-NEXT: orr r0, r0, #8960 197; CHECK-ARM-NEXT: orr r0, r0, #2293760 198; CHECK-ARM-NEXT: mov pc, lr 199; 200; CHECK-THUMB2-LABEL: orr0: 201; CHECK-THUMB2: @ %bb.0: 202; CHECK-THUMB2-NEXT: orr r0, r0, #2293760 203; CHECK-THUMB2-NEXT: orr r0, r0, #8960 204; CHECK-THUMB2-NEXT: bx lr 205 %2 = or i32 %0, 2302720 206 ret i32 %2 207} 208 209define i32 @orr1(i32 %0) { 210; CHECK-ARM-LABEL: orr1: 211; CHECK-ARM: @ %bb.0: 212; CHECK-ARM-NEXT: orr r0, r0, #23 213; CHECK-ARM-NEXT: mov pc, lr 214; 215; CHECK-THUMB2-LABEL: orr1: 216; CHECK-THUMB2: @ %bb.0: 217; CHECK-THUMB2-NEXT: orr r0, r0, #23 218; CHECK-THUMB2-NEXT: bx lr 219 %2 = or i32 %0, 23 220 ret i32 %2 221} 222 223define i32 @orr2(i32 %0) { 224; CHECK-ARM-LABEL: orr2: 225; CHECK-ARM: @ %bb.0: 226; CHECK-ARM-NEXT: ldr r1, .LCPI12_0 227; CHECK-ARM-NEXT: orr r0, r0, r1 228; CHECK-ARM-NEXT: mov pc, lr 229; CHECK-ARM-NEXT: .p2align 2 230; CHECK-ARM-NEXT: @ %bb.1: 231; CHECK-ARM-NEXT: .LCPI12_0: 232; CHECK-ARM-NEXT: .long 131071 @ 0x1ffff 233; 234; CHECK-THUMB2-LABEL: orr2: 235; CHECK-THUMB2: @ %bb.0: 236; CHECK-THUMB2-NEXT: movw r1, #65535 237; CHECK-THUMB2-NEXT: movt r1, #1 238; CHECK-THUMB2-NEXT: orrs r0, r1 239; CHECK-THUMB2-NEXT: bx lr 240 %2 = or i32 %0, 131071 241 ret i32 %2 242} 243 244define i32 @eor0(i32 %0) { 245; CHECK-ARM-LABEL: eor0: 246; CHECK-ARM: @ %bb.0: 247; CHECK-ARM-NEXT: eor r0, r0, #8960 248; CHECK-ARM-NEXT: eor r0, r0, #2293760 249; CHECK-ARM-NEXT: mov pc, lr 250; 251; CHECK-THUMB2-LABEL: eor0: 252; CHECK-THUMB2: @ %bb.0: 253; CHECK-THUMB2-NEXT: eor r0, r0, #2293760 254; CHECK-THUMB2-NEXT: eor r0, r0, #8960 255; CHECK-THUMB2-NEXT: bx lr 256 %2 = xor i32 %0, 2302720 257 ret i32 %2 258} 259 260define i32 @eor1(i32 %0) { 261; CHECK-ARM-LABEL: eor1: 262; CHECK-ARM: @ %bb.0: 263; CHECK-ARM-NEXT: eor r0, r0, #23 264; CHECK-ARM-NEXT: mov pc, lr 265; 266; CHECK-THUMB2-LABEL: eor1: 267; CHECK-THUMB2: @ %bb.0: 268; CHECK-THUMB2-NEXT: eor r0, r0, #23 269; CHECK-THUMB2-NEXT: bx lr 270 %2 = xor i32 %0, 23 271 ret i32 %2 272} 273 274define i32 @eor2(i32 %0) { 275; CHECK-ARM-LABEL: eor2: 276; CHECK-ARM: @ %bb.0: 277; CHECK-ARM-NEXT: ldr r1, .LCPI15_0 278; CHECK-ARM-NEXT: eor r0, r0, r1 279; CHECK-ARM-NEXT: mov pc, lr 280; CHECK-ARM-NEXT: .p2align 2 281; CHECK-ARM-NEXT: @ %bb.1: 282; CHECK-ARM-NEXT: .LCPI15_0: 283; CHECK-ARM-NEXT: .long 131071 @ 0x1ffff 284; 285; CHECK-THUMB2-LABEL: eor2: 286; CHECK-THUMB2: @ %bb.0: 287; CHECK-THUMB2-NEXT: movw r1, #65535 288; CHECK-THUMB2-NEXT: movt r1, #1 289; CHECK-THUMB2-NEXT: eors r0, r1 290; CHECK-THUMB2-NEXT: bx lr 291 %2 = xor i32 %0, 131071 292 ret i32 %2 293} 294