xref: /llvm-project/llvm/test/CodeGen/ARM/sxt_rot.ll (revision 4a5e1ffcf9b8fe2f57112aca2f0223b4a9c8773b) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V6
3; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V7
4
5define i32 @test0(i8 %A) {
6; CHECK-LABEL: test0:
7; CHECK:       @ %bb.0:
8; CHECK-NEXT:    sxtb r0, r0
9; CHECK-NEXT:    bx lr
10  %B = sext i8 %A to i32
11  ret i32 %B
12}
13
14define signext i8 @test1(i32 %A) {
15; CHECK-V6-LABEL: test1:
16; CHECK-V6:       @ %bb.0:
17; CHECK-V6-NEXT:    lsr r0, r0, #8
18; CHECK-V6-NEXT:    sxtb r0, r0
19; CHECK-V6-NEXT:    bx lr
20;
21; CHECK-V7-LABEL: test1:
22; CHECK-V7:       @ %bb.0:
23; CHECK-V7-NEXT:    sbfx r0, r0, #8, #8
24; CHECK-V7-NEXT:    bx lr
25; CHECk-V7: sbfx r0, r0, #8, #8
26  %B = lshr i32 %A, 8
27  %C = shl i32 %A, 24
28  %D = or i32 %B, %C
29  %E = trunc i32 %D to i8
30  ret i8 %E
31}
32
33define signext i32 @test2(i32 %A, i32 %X) {
34; CHECK-LABEL: test2:
35; CHECK:       @ %bb.0:
36; CHECK-NEXT:    sxtab r0, r1, r0, ror #8
37; CHECK-NEXT:    bx lr
38  %B = lshr i32 %A, 8
39  %C = shl i32 %A, 24
40  %D = or i32 %B, %C
41  %E = trunc i32 %D to i8
42  %F = sext i8 %E to i32
43  %G = add i32 %F, %X
44  ret i32 %G
45}
46
47define signext i32 @test3(i32 %A, i32 %X) {
48; CHECK-LABEL: test3:
49; CHECK:       @ %bb.0:
50; CHECK-NEXT:    sxtab r0, r1, r0, ror #16
51; CHECK-NEXT:    bx lr
52  %B = lshr i32 %A, 16
53  %C = shl i32 %A, 16
54  %D = or i32 %B, %C
55  %E = trunc i32 %D to i8
56  %F = sext i8 %E to i32
57  %G = add i32 %F, %X
58  ret i32 %G
59}
60
61define signext i32 @test4(i32 %A, i32 %X) {
62; CHECK-LABEL: test4:
63; CHECK:       @ %bb.0:
64; CHECK-NEXT:    sxtah r0, r1, r0, ror #8
65; CHECK-NEXT:    bx lr
66  %B = lshr i32 %A, 8
67  %C = shl i32 %A, 24
68  %D = or i32 %B, %C
69  %E = trunc i32 %D to i16
70  %F = sext i16 %E to i32
71  %G = add i32 %F, %X
72  ret i32 %G
73}
74
75define signext i32 @test5(i32 %A, i32 %X) {
76; CHECK-LABEL: test5:
77; CHECK:       @ %bb.0:
78; CHECK-NEXT:    sxtah r0, r1, r0, ror #24
79; CHECK-NEXT:    bx lr
80  %B = lshr i32 %A, 24
81  %C = shl i32 %A, 8
82  %D = or i32 %B, %C
83  %E = trunc i32 %D to i16
84  %F = sext i16 %E to i32
85  %G = add i32 %F, %X
86  ret i32 %G
87}
88
89define i32 @test6(i8 %A, i32 %X) {
90; CHECK-LABEL: test6:
91; CHECK:       @ %bb.0:
92; CHECK-NEXT:    sxtab r0, r1, r0
93; CHECK-NEXT:    bx lr
94  %sext = sext i8 %A to i32
95  %add = add i32 %X, %sext
96  ret i32 %add
97}
98
99define i32 @test7(i32 %A, i32 %X) {
100; CHECK-LABEL: test7:
101; CHECK:       @ %bb.0:
102; CHECK-NEXT:    sxtab r0, r1, r0
103; CHECK-NEXT:    bx lr
104  %shl = shl i32 %A, 24
105  %shr = ashr i32 %shl, 24
106  %add = add i32 %X, %shr
107  ret i32 %add
108}
109
110define i32 @test8(i16 %A, i32 %X) {
111; CHECK-LABEL: test8:
112; CHECK:       @ %bb.0:
113; CHECK-NEXT:    sxtah r0, r1, r0
114; CHECK-NEXT:    bx lr
115  %sext = sext i16 %A to i32
116  %add = add i32 %X, %sext
117  ret i32 %add
118}
119
120define i32 @test9(i32 %A, i32 %X) {
121; CHECK-LABEL: test9:
122; CHECK:       @ %bb.0:
123; CHECK-NEXT:    sxtah r0, r1, r0
124; CHECK-NEXT:    bx lr
125  %shl = shl i32 %A, 16
126  %shr = ashr i32 %shl, 16
127  %add = add i32 %X, %shr
128  ret i32 %add
129}
130