1; RUN: llc -mtriple=arm-linux-gnueabihf -filetype=obj <%s | llvm-objdump --triple=armv7 --no-show-raw-insn -d - | FileCheck %s 2 3;; Expect architectural nop to be used between func2 and func3 but not func1 4;; and func2 due to lack of subtarget support in func2. 5 6define i32 @func1() #0 align 16 { 7entry: 8 ret i32 0 9} 10 11define i32 @func2() #1 align 16 { 12entry: 13 ret i32 0 14} 15 16define i32 @func3() #0 align 16 { 17entry: 18 ret i32 0 19} 20 21attributes #0 = { "target-cpu"="generic" "target-features"="+armv7-a,+dsp,+neon,+vfp3,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" } 22attributes #1 = { "target-cpu"="arm7tdmi" "target-features"="+armv4t" "use-soft-float"="true" } 23 24 25; CHECK: 00000000 <func1>: 26; CHECK-NEXT: 0: mov r0, #0 27; CHECK-NEXT: 4: bx lr 28; CHECK-NEXT: 8: mov r0, r0 29; CHECK-NEXT: c: mov r0, r0 30 31; CHECK: 00000010 <func2>: 32; CHECK-NEXT: 10: mov r0, #0 33; CHECK-NEXT: 14: bx lr 34; CHECK-NEXT: 18: nop 35; CHECK-NEXT: 1c: nop 36 37; CHECK: 00000020 <func3>: 38; CHECK-NEXT: 20: mov r0, #0 39; CHECK-NEXT: 24: bx lr 40