1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1 3; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP 4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP 5; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS 6; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP 7; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP 8 9declare i4 @llvm.ssub.sat.i4(i4, i4) 10declare i8 @llvm.ssub.sat.i8(i8, i8) 11declare i16 @llvm.ssub.sat.i16(i16, i16) 12declare i32 @llvm.ssub.sat.i32(i32, i32) 13declare i64 @llvm.ssub.sat.i64(i64, i64) 14declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) 15 16define i32 @func(i32 %x, i32 %y) nounwind { 17; CHECK-T1-LABEL: func: 18; CHECK-T1: @ %bb.0: 19; CHECK-T1-NEXT: subs r0, r0, r1 20; CHECK-T1-NEXT: bvc .LBB0_2 21; CHECK-T1-NEXT: @ %bb.1: 22; CHECK-T1-NEXT: asrs r1, r0, #31 23; CHECK-T1-NEXT: movs r0, #1 24; CHECK-T1-NEXT: lsls r0, r0, #31 25; CHECK-T1-NEXT: eors r0, r1 26; CHECK-T1-NEXT: .LBB0_2: 27; CHECK-T1-NEXT: bx lr 28; 29; CHECK-T2NODSP-LABEL: func: 30; CHECK-T2NODSP: @ %bb.0: 31; CHECK-T2NODSP-NEXT: subs r0, r0, r1 32; CHECK-T2NODSP-NEXT: mov.w r1, #-2147483648 33; CHECK-T2NODSP-NEXT: it vs 34; CHECK-T2NODSP-NEXT: eorvs.w r0, r1, r0, asr #31 35; CHECK-T2NODSP-NEXT: bx lr 36; 37; CHECK-T2DSP-LABEL: func: 38; CHECK-T2DSP: @ %bb.0: 39; CHECK-T2DSP-NEXT: qsub r0, r0, r1 40; CHECK-T2DSP-NEXT: bx lr 41; 42; CHECK-ARMNODPS-LABEL: func: 43; CHECK-ARMNODPS: @ %bb.0: 44; CHECK-ARMNODPS-NEXT: subs r0, r0, r1 45; CHECK-ARMNODPS-NEXT: mov r1, #-2147483648 46; CHECK-ARMNODPS-NEXT: eorvs r0, r1, r0, asr #31 47; CHECK-ARMNODPS-NEXT: bx lr 48; 49; CHECK-ARMBASEDSP-LABEL: func: 50; CHECK-ARMBASEDSP: @ %bb.0: 51; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1 52; CHECK-ARMBASEDSP-NEXT: bx lr 53; 54; CHECK-ARMDSP-LABEL: func: 55; CHECK-ARMDSP: @ %bb.0: 56; CHECK-ARMDSP-NEXT: qsub r0, r0, r1 57; CHECK-ARMDSP-NEXT: bx lr 58 %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y) 59 ret i32 %tmp 60} 61 62define i64 @func2(i64 %x, i64 %y) nounwind { 63; CHECK-T1-LABEL: func2: 64; CHECK-T1: @ %bb.0: 65; CHECK-T1-NEXT: .save {r4, r5, r7, lr} 66; CHECK-T1-NEXT: push {r4, r5, r7, lr} 67; CHECK-T1-NEXT: mov r4, r1 68; CHECK-T1-NEXT: eors r1, r3 69; CHECK-T1-NEXT: subs r5, r0, r2 70; CHECK-T1-NEXT: mov r2, r4 71; CHECK-T1-NEXT: sbcs r2, r3 72; CHECK-T1-NEXT: eors r4, r2 73; CHECK-T1-NEXT: ands r4, r1 74; CHECK-T1-NEXT: asrs r0, r2, #31 75; CHECK-T1-NEXT: movs r1, #1 76; CHECK-T1-NEXT: lsls r1, r1, #31 77; CHECK-T1-NEXT: eors r1, r0 78; CHECK-T1-NEXT: cmp r4, #0 79; CHECK-T1-NEXT: bpl .LBB1_3 80; CHECK-T1-NEXT: @ %bb.1: 81; CHECK-T1-NEXT: bpl .LBB1_4 82; CHECK-T1-NEXT: .LBB1_2: 83; CHECK-T1-NEXT: pop {r4, r5, r7, pc} 84; CHECK-T1-NEXT: .LBB1_3: 85; CHECK-T1-NEXT: mov r0, r5 86; CHECK-T1-NEXT: bmi .LBB1_2 87; CHECK-T1-NEXT: .LBB1_4: 88; CHECK-T1-NEXT: mov r1, r2 89; CHECK-T1-NEXT: pop {r4, r5, r7, pc} 90; 91; CHECK-T2-LABEL: func2: 92; CHECK-T2: @ %bb.0: 93; CHECK-T2-NEXT: subs r0, r0, r2 94; CHECK-T2-NEXT: eor.w r12, r1, r3 95; CHECK-T2-NEXT: sbc.w r2, r1, r3 96; CHECK-T2-NEXT: eors r1, r2 97; CHECK-T2-NEXT: ands.w r1, r1, r12 98; CHECK-T2-NEXT: it mi 99; CHECK-T2-NEXT: asrmi r0, r2, #31 100; CHECK-T2-NEXT: mov.w r1, #-2147483648 101; CHECK-T2-NEXT: it mi 102; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31 103; CHECK-T2-NEXT: mov r1, r2 104; CHECK-T2-NEXT: bx lr 105; 106; CHECK-ARM-LABEL: func2: 107; CHECK-ARM: @ %bb.0: 108; CHECK-ARM-NEXT: subs r0, r0, r2 109; CHECK-ARM-NEXT: eor r12, r1, r3 110; CHECK-ARM-NEXT: sbc r2, r1, r3 111; CHECK-ARM-NEXT: eor r1, r1, r2 112; CHECK-ARM-NEXT: ands r1, r12, r1 113; CHECK-ARM-NEXT: asrmi r0, r2, #31 114; CHECK-ARM-NEXT: mov r1, #-2147483648 115; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31 116; CHECK-ARM-NEXT: mov r1, r2 117; CHECK-ARM-NEXT: bx lr 118 %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y) 119 ret i64 %tmp 120} 121 122define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind { 123; CHECK-T1-LABEL: func16: 124; CHECK-T1: @ %bb.0: 125; CHECK-T1-NEXT: subs r0, r0, r1 126; CHECK-T1-NEXT: ldr r1, .LCPI2_0 127; CHECK-T1-NEXT: cmp r0, r1 128; CHECK-T1-NEXT: blt .LBB2_2 129; CHECK-T1-NEXT: @ %bb.1: 130; CHECK-T1-NEXT: mov r0, r1 131; CHECK-T1-NEXT: .LBB2_2: 132; CHECK-T1-NEXT: ldr r1, .LCPI2_1 133; CHECK-T1-NEXT: cmp r0, r1 134; CHECK-T1-NEXT: bgt .LBB2_4 135; CHECK-T1-NEXT: @ %bb.3: 136; CHECK-T1-NEXT: mov r0, r1 137; CHECK-T1-NEXT: .LBB2_4: 138; CHECK-T1-NEXT: bx lr 139; CHECK-T1-NEXT: .p2align 2 140; CHECK-T1-NEXT: @ %bb.5: 141; CHECK-T1-NEXT: .LCPI2_0: 142; CHECK-T1-NEXT: .long 32767 @ 0x7fff 143; CHECK-T1-NEXT: .LCPI2_1: 144; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000 145; 146; CHECK-T2NODSP-LABEL: func16: 147; CHECK-T2NODSP: @ %bb.0: 148; CHECK-T2NODSP-NEXT: subs r0, r0, r1 149; CHECK-T2NODSP-NEXT: ssat r0, #16, r0 150; CHECK-T2NODSP-NEXT: bx lr 151; 152; CHECK-T2DSP-LABEL: func16: 153; CHECK-T2DSP: @ %bb.0: 154; CHECK-T2DSP-NEXT: qsub16 r0, r0, r1 155; CHECK-T2DSP-NEXT: sxth r0, r0 156; CHECK-T2DSP-NEXT: bx lr 157; 158; CHECK-ARMNODPS-LABEL: func16: 159; CHECK-ARMNODPS: @ %bb.0: 160; CHECK-ARMNODPS-NEXT: sub r0, r0, r1 161; CHECK-ARMNODPS-NEXT: mov r1, #255 162; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512 163; CHECK-ARMNODPS-NEXT: cmp r0, r1 164; CHECK-ARMNODPS-NEXT: movlt r1, r0 165; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0 166; CHECK-ARMNODPS-NEXT: cmn r1, #32768 167; CHECK-ARMNODPS-NEXT: movgt r0, r1 168; CHECK-ARMNODPS-NEXT: bx lr 169; CHECK-ARMNODPS-NEXT: .p2align 2 170; CHECK-ARMNODPS-NEXT: @ %bb.1: 171; CHECK-ARMNODPS-NEXT: .LCPI2_0: 172; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000 173; 174; CHECK-ARMBASEDSP-LABEL: func16: 175; CHECK-ARMBASEDSP: @ %bb.0: 176; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #16 177; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #16 178; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1 179; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #16 180; CHECK-ARMBASEDSP-NEXT: bx lr 181; 182; CHECK-ARMDSP-LABEL: func16: 183; CHECK-ARMDSP: @ %bb.0: 184; CHECK-ARMDSP-NEXT: qsub16 r0, r0, r1 185; CHECK-ARMDSP-NEXT: sxth r0, r0 186; CHECK-ARMDSP-NEXT: bx lr 187 %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y) 188 ret i16 %tmp 189} 190 191define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind { 192; CHECK-T1-LABEL: func8: 193; CHECK-T1: @ %bb.0: 194; CHECK-T1-NEXT: subs r0, r0, r1 195; CHECK-T1-NEXT: movs r1, #127 196; CHECK-T1-NEXT: cmp r0, #127 197; CHECK-T1-NEXT: blt .LBB3_2 198; CHECK-T1-NEXT: @ %bb.1: 199; CHECK-T1-NEXT: mov r0, r1 200; CHECK-T1-NEXT: .LBB3_2: 201; CHECK-T1-NEXT: mvns r1, r1 202; CHECK-T1-NEXT: cmp r0, r1 203; CHECK-T1-NEXT: bgt .LBB3_4 204; CHECK-T1-NEXT: @ %bb.3: 205; CHECK-T1-NEXT: mov r0, r1 206; CHECK-T1-NEXT: .LBB3_4: 207; CHECK-T1-NEXT: bx lr 208; 209; CHECK-T2NODSP-LABEL: func8: 210; CHECK-T2NODSP: @ %bb.0: 211; CHECK-T2NODSP-NEXT: subs r0, r0, r1 212; CHECK-T2NODSP-NEXT: ssat r0, #8, r0 213; CHECK-T2NODSP-NEXT: bx lr 214; 215; CHECK-T2DSP-LABEL: func8: 216; CHECK-T2DSP: @ %bb.0: 217; CHECK-T2DSP-NEXT: qsub8 r0, r0, r1 218; CHECK-T2DSP-NEXT: sxtb r0, r0 219; CHECK-T2DSP-NEXT: bx lr 220; 221; CHECK-ARMNODPS-LABEL: func8: 222; CHECK-ARMNODPS: @ %bb.0: 223; CHECK-ARMNODPS-NEXT: sub r0, r0, r1 224; CHECK-ARMNODPS-NEXT: cmp r0, #127 225; CHECK-ARMNODPS-NEXT: movge r0, #127 226; CHECK-ARMNODPS-NEXT: cmn r0, #128 227; CHECK-ARMNODPS-NEXT: mvnle r0, #127 228; CHECK-ARMNODPS-NEXT: bx lr 229; 230; CHECK-ARMBASEDSP-LABEL: func8: 231; CHECK-ARMBASEDSP: @ %bb.0: 232; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #24 233; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #24 234; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1 235; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #24 236; CHECK-ARMBASEDSP-NEXT: bx lr 237; 238; CHECK-ARMDSP-LABEL: func8: 239; CHECK-ARMDSP: @ %bb.0: 240; CHECK-ARMDSP-NEXT: qsub8 r0, r0, r1 241; CHECK-ARMDSP-NEXT: sxtb r0, r0 242; CHECK-ARMDSP-NEXT: bx lr 243 %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y) 244 ret i8 %tmp 245} 246 247define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind { 248; CHECK-T1-LABEL: func3: 249; CHECK-T1: @ %bb.0: 250; CHECK-T1-NEXT: subs r0, r0, r1 251; CHECK-T1-NEXT: movs r1, #7 252; CHECK-T1-NEXT: cmp r0, #7 253; CHECK-T1-NEXT: blt .LBB4_2 254; CHECK-T1-NEXT: @ %bb.1: 255; CHECK-T1-NEXT: mov r0, r1 256; CHECK-T1-NEXT: .LBB4_2: 257; CHECK-T1-NEXT: mvns r1, r1 258; CHECK-T1-NEXT: cmp r0, r1 259; CHECK-T1-NEXT: bgt .LBB4_4 260; CHECK-T1-NEXT: @ %bb.3: 261; CHECK-T1-NEXT: mov r0, r1 262; CHECK-T1-NEXT: .LBB4_4: 263; CHECK-T1-NEXT: bx lr 264; 265; CHECK-T2NODSP-LABEL: func3: 266; CHECK-T2NODSP: @ %bb.0: 267; CHECK-T2NODSP-NEXT: subs r0, r0, r1 268; CHECK-T2NODSP-NEXT: ssat r0, #4, r0 269; CHECK-T2NODSP-NEXT: bx lr 270; 271; CHECK-T2DSP-LABEL: func3: 272; CHECK-T2DSP: @ %bb.0: 273; CHECK-T2DSP-NEXT: lsls r1, r1, #28 274; CHECK-T2DSP-NEXT: lsls r0, r0, #28 275; CHECK-T2DSP-NEXT: qsub r0, r0, r1 276; CHECK-T2DSP-NEXT: asrs r0, r0, #28 277; CHECK-T2DSP-NEXT: bx lr 278; 279; CHECK-ARMNODPS-LABEL: func3: 280; CHECK-ARMNODPS: @ %bb.0: 281; CHECK-ARMNODPS-NEXT: sub r0, r0, r1 282; CHECK-ARMNODPS-NEXT: cmp r0, #7 283; CHECK-ARMNODPS-NEXT: movge r0, #7 284; CHECK-ARMNODPS-NEXT: cmn r0, #8 285; CHECK-ARMNODPS-NEXT: mvnle r0, #7 286; CHECK-ARMNODPS-NEXT: bx lr 287; 288; CHECK-ARMBASEDSP-LABEL: func3: 289; CHECK-ARMBASEDSP: @ %bb.0: 290; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #28 291; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #28 292; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1 293; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #28 294; CHECK-ARMBASEDSP-NEXT: bx lr 295; 296; CHECK-ARMDSP-LABEL: func3: 297; CHECK-ARMDSP: @ %bb.0: 298; CHECK-ARMDSP-NEXT: lsl r0, r0, #28 299; CHECK-ARMDSP-NEXT: lsl r1, r1, #28 300; CHECK-ARMDSP-NEXT: qsub r0, r0, r1 301; CHECK-ARMDSP-NEXT: asr r0, r0, #28 302; CHECK-ARMDSP-NEXT: bx lr 303 %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y) 304 ret i4 %tmp 305} 306 307define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { 308; CHECK-T1-LABEL: vec: 309; CHECK-T1: @ %bb.0: 310; CHECK-T1-NEXT: .save {r4, r5, r6, lr} 311; CHECK-T1-NEXT: push {r4, r5, r6, lr} 312; CHECK-T1-NEXT: mov r4, r0 313; CHECK-T1-NEXT: ldr r6, [sp, #16] 314; CHECK-T1-NEXT: subs r0, r0, r6 315; CHECK-T1-NEXT: movs r5, #1 316; CHECK-T1-NEXT: lsls r5, r5, #31 317; CHECK-T1-NEXT: cmp r4, r6 318; CHECK-T1-NEXT: bvc .LBB5_2 319; CHECK-T1-NEXT: @ %bb.1: 320; CHECK-T1-NEXT: asrs r0, r0, #31 321; CHECK-T1-NEXT: eors r0, r5 322; CHECK-T1-NEXT: .LBB5_2: 323; CHECK-T1-NEXT: ldr r4, [sp, #20] 324; CHECK-T1-NEXT: subs r1, r1, r4 325; CHECK-T1-NEXT: bvc .LBB5_4 326; CHECK-T1-NEXT: @ %bb.3: 327; CHECK-T1-NEXT: asrs r1, r1, #31 328; CHECK-T1-NEXT: eors r1, r5 329; CHECK-T1-NEXT: .LBB5_4: 330; CHECK-T1-NEXT: ldr r4, [sp, #24] 331; CHECK-T1-NEXT: subs r2, r2, r4 332; CHECK-T1-NEXT: bvc .LBB5_6 333; CHECK-T1-NEXT: @ %bb.5: 334; CHECK-T1-NEXT: asrs r2, r2, #31 335; CHECK-T1-NEXT: eors r2, r5 336; CHECK-T1-NEXT: .LBB5_6: 337; CHECK-T1-NEXT: ldr r4, [sp, #28] 338; CHECK-T1-NEXT: subs r3, r3, r4 339; CHECK-T1-NEXT: bvc .LBB5_8 340; CHECK-T1-NEXT: @ %bb.7: 341; CHECK-T1-NEXT: asrs r3, r3, #31 342; CHECK-T1-NEXT: eors r3, r5 343; CHECK-T1-NEXT: .LBB5_8: 344; CHECK-T1-NEXT: pop {r4, r5, r6, pc} 345; 346; CHECK-T2NODSP-LABEL: vec: 347; CHECK-T2NODSP: @ %bb.0: 348; CHECK-T2NODSP-NEXT: .save {r7, lr} 349; CHECK-T2NODSP-NEXT: push {r7, lr} 350; CHECK-T2NODSP-NEXT: ldr.w r12, [sp, #8] 351; CHECK-T2NODSP-NEXT: ldr.w lr, [sp, #12] 352; CHECK-T2NODSP-NEXT: subs.w r0, r0, r12 353; CHECK-T2NODSP-NEXT: mov.w r12, #-2147483648 354; CHECK-T2NODSP-NEXT: it vs 355; CHECK-T2NODSP-NEXT: eorvs.w r0, r12, r0, asr #31 356; CHECK-T2NODSP-NEXT: subs.w r1, r1, lr 357; CHECK-T2NODSP-NEXT: ldr.w lr, [sp, #16] 358; CHECK-T2NODSP-NEXT: it vs 359; CHECK-T2NODSP-NEXT: eorvs.w r1, r12, r1, asr #31 360; CHECK-T2NODSP-NEXT: subs.w r2, r2, lr 361; CHECK-T2NODSP-NEXT: ldr.w lr, [sp, #20] 362; CHECK-T2NODSP-NEXT: it vs 363; CHECK-T2NODSP-NEXT: eorvs.w r2, r12, r2, asr #31 364; CHECK-T2NODSP-NEXT: subs.w r3, r3, lr 365; CHECK-T2NODSP-NEXT: it vs 366; CHECK-T2NODSP-NEXT: eorvs.w r3, r12, r3, asr #31 367; CHECK-T2NODSP-NEXT: pop {r7, pc} 368; 369; CHECK-T2DSP-LABEL: vec: 370; CHECK-T2DSP: @ %bb.0: 371; CHECK-T2DSP-NEXT: ldr.w r12, [sp] 372; CHECK-T2DSP-NEXT: qsub r0, r0, r12 373; CHECK-T2DSP-NEXT: ldr.w r12, [sp, #4] 374; CHECK-T2DSP-NEXT: qsub r1, r1, r12 375; CHECK-T2DSP-NEXT: ldr.w r12, [sp, #8] 376; CHECK-T2DSP-NEXT: qsub r2, r2, r12 377; CHECK-T2DSP-NEXT: ldr.w r12, [sp, #12] 378; CHECK-T2DSP-NEXT: qsub r3, r3, r12 379; CHECK-T2DSP-NEXT: bx lr 380; 381; CHECK-ARMNODPS-LABEL: vec: 382; CHECK-ARMNODPS: @ %bb.0: 383; CHECK-ARMNODPS-NEXT: .save {r11, lr} 384; CHECK-ARMNODPS-NEXT: push {r11, lr} 385; CHECK-ARMNODPS-NEXT: ldr r12, [sp, #8] 386; CHECK-ARMNODPS-NEXT: ldr lr, [sp, #12] 387; CHECK-ARMNODPS-NEXT: subs r0, r0, r12 388; CHECK-ARMNODPS-NEXT: mov r12, #-2147483648 389; CHECK-ARMNODPS-NEXT: eorvs r0, r12, r0, asr #31 390; CHECK-ARMNODPS-NEXT: subs r1, r1, lr 391; CHECK-ARMNODPS-NEXT: ldr lr, [sp, #16] 392; CHECK-ARMNODPS-NEXT: eorvs r1, r12, r1, asr #31 393; CHECK-ARMNODPS-NEXT: subs r2, r2, lr 394; CHECK-ARMNODPS-NEXT: ldr lr, [sp, #20] 395; CHECK-ARMNODPS-NEXT: eorvs r2, r12, r2, asr #31 396; CHECK-ARMNODPS-NEXT: subs r3, r3, lr 397; CHECK-ARMNODPS-NEXT: eorvs r3, r12, r3, asr #31 398; CHECK-ARMNODPS-NEXT: pop {r11, pc} 399; 400; CHECK-ARMBASEDSP-LABEL: vec: 401; CHECK-ARMBASEDSP: @ %bb.0: 402; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp] 403; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r12 404; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp, #4] 405; CHECK-ARMBASEDSP-NEXT: qsub r1, r1, r12 406; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp, #8] 407; CHECK-ARMBASEDSP-NEXT: qsub r2, r2, r12 408; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp, #12] 409; CHECK-ARMBASEDSP-NEXT: qsub r3, r3, r12 410; CHECK-ARMBASEDSP-NEXT: bx lr 411; 412; CHECK-ARMDSP-LABEL: vec: 413; CHECK-ARMDSP: @ %bb.0: 414; CHECK-ARMDSP-NEXT: ldr r12, [sp] 415; CHECK-ARMDSP-NEXT: qsub r0, r0, r12 416; CHECK-ARMDSP-NEXT: ldr r12, [sp, #4] 417; CHECK-ARMDSP-NEXT: qsub r1, r1, r12 418; CHECK-ARMDSP-NEXT: ldr r12, [sp, #8] 419; CHECK-ARMDSP-NEXT: qsub r2, r2, r12 420; CHECK-ARMDSP-NEXT: ldr r12, [sp, #12] 421; CHECK-ARMDSP-NEXT: qsub r3, r3, r12 422; CHECK-ARMDSP-NEXT: bx lr 423 %tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y) 424 ret <4 x i32> %tmp 425} 426