xref: /llvm-project/llvm/test/CodeGen/ARM/spill-q.ll (revision bed1c7f061aa12417aa081e334afdba45767b938) 
1; RUN: llc < %s -mtriple=armv7-elf -mattr=+neon -arm-atomic-cfg-tidy=0 | FileCheck %s
2; PR4789
3
4%bar = type { float, float, float }
5%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
6%foo = type { <4 x float> }
7%quux = type { ptr, ptr, i32 }
8%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
9
10declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly
11
12define void @aaa(ptr %this, ptr %block) {
13; CHECK-LABEL: aaa:
14; CHECK: bfc {{.*}}, #0, #4
15; CHECK: vst1.64 {{.*}}sp:128
16; CHECK: vld1.64 {{.*}}sp:128
17entry:
18  %aligned_vec = alloca <4 x float>, align 16
19  %"alloca point" = bitcast i32 0 to i32
20  %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %aligned_vec, i32 1) nounwind ; <<4 x float>> [#uses=1]
21  store float 6.300000e+01, ptr undef, align 4
22  %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
23  store float 0.000000e+00, ptr undef, align 4
24  %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
25  %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
26  store float 0.000000e+00, ptr undef, align 4
27  %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
28  store float 0.000000e+00, ptr undef, align 4
29  %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
30  store float 0.000000e+00, ptr undef, align 4
31  %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
32  store float 0.000000e+00, ptr undef, align 4
33  %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
34  store float 0.000000e+00, ptr undef, align 4
35  %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
36  store float 0.000000e+00, ptr undef, align 4
37  %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
38  store float 0.000000e+00, ptr undef, align 4
39  %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
40  store float 0.000000e+00, ptr undef, align 4
41  %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
42  store float 0.000000e+00, ptr undef, align 4
43  %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
44  store float 0.000000e+00, ptr undef, align 4
45  %val173 = load <4 x float>, ptr undef               ; <<4 x float>> [#uses=1]
46  br label %bb4
47
48bb4:                                              ; preds = %bb193, %entry
49  %besterror.0.2264 = phi <4 x float> [ undef, %entry ], [ %besterror.0.0, %bb193 ] ; <<4 x float>> [#uses=2]
50  %part0.0.0261 = phi <4 x float> [ zeroinitializer, %entry ], [ %23, %bb193 ] ; <<4 x float>> [#uses=2]
51  %3 = fmul <4 x float> zeroinitializer, %0       ; <<4 x float>> [#uses=2]
52  %4 = fadd <4 x float> %3, %part0.0.0261         ; <<4 x float>> [#uses=1]
53  %5 = shufflevector <4 x float> %3, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
54  %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
55  %7 = fmul <4 x float> %1, %1
56  %8 = fadd <4 x float> %7, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]
57  %9 = fptosi <4 x float> %8 to <4 x i32>         ; <<4 x i32>> [#uses=1]
58  %10 = sitofp <4 x i32> %9 to <4 x float>        ; <<4 x float>> [#uses=1]
59  %11 = fmul <4 x float> %10, %2                  ; <<4 x float>> [#uses=1]
60  %12 = fmul <4 x float> %6, %6
61  %13 = fmul <4 x float> %11, %4                  ; <<4 x float>> [#uses=1]
62  %14 = fsub <4 x float> %12, %13                 ; <<4 x float>> [#uses=1]
63  %15 = fsub <4 x float> %14, %14
64  %16 = fmul <4 x float> %15, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1]
65  %17 = fadd <4 x float> %16, %16
66  %18 = fmul <4 x float> %17, %val173             ; <<4 x float>> [#uses=1]
67  %19 = shufflevector <4 x float> %18, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
68  %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
69  %tmp1 = fadd <4 x float> %20, %ld3
70  %tmp2 = fadd <4 x float> %tmp1, %ld4
71  %tmp3 = fadd <4 x float> %tmp2, %ld5
72  %tmp4 = fadd <4 x float> %tmp3, %ld6
73  %tmp5 = fadd <4 x float> %tmp4, %ld7
74  %tmp6 = fadd <4 x float> %tmp5, %ld8
75  %tmp7 = fadd <4 x float> %tmp6, %ld9
76  %tmp8 = fadd <4 x float> %tmp7, %ld10
77  %tmp9 = fadd <4 x float> %tmp8, %ld11
78  %21 = fadd <4 x float> %tmp9, %ld12
79  %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0]
80  %tmp = extractelement <4 x i1> %22, i32 0
81  br i1 %tmp, label %bb193, label %bb186
82
83bb186:                                            ; preds = %bb4
84  br label %bb193
85
86bb193:                                            ; preds = %bb186, %bb4
87  %besterror.0.0 = phi <4 x float> [ %21, %bb186 ], [ %besterror.0.2264, %bb4 ] ; <<4 x float>> [#uses=1]
88  %23 = fadd <4 x float> %part0.0.0261, zeroinitializer ; <<4 x float>> [#uses=1]
89  br label %bb4
90}
91