xref: /llvm-project/llvm/test/CodeGen/ARM/signext-inreg.ll (revision 7863cc6c1c9e714de666f7df84fe9ef6ea7bb06c)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=armv8 | FileCheck %s
3; RUN: llc < %s -mtriple=armv8 -early-live-intervals -verify-machineinstrs | FileCheck %s
4define <4 x i32> @test(<4 x i32> %m) {
5; CHECK-LABEL: test:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vmov d17, r2, r3
8; CHECK-NEXT:    vmov d16, r0, r1
9; CHECK-NEXT:    vshl.i32 q8, q8, #24
10; CHECK-NEXT:    vshr.s32 q8, q8, #24
11; CHECK-NEXT:    vmov r0, r1, d16
12; CHECK-NEXT:    vmov r2, r3, d17
13; CHECK-NEXT:    bx lr
14entry:
15  %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
16  %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
17  ret <4 x i32> %shr
18}
19