xref: /llvm-project/llvm/test/CodeGen/ARM/ror.ll (revision b432f80e48a005b47cee7bb86bc9ec9cc861b705) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
3
4; rotr (rotr x, 4), 6 -> rotr x, 10 -> ror r0, r0, #10
5define i32 @test1(i32 %x) nounwind readnone {
6; CHECK-LABEL: test1:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    ror r0, r0, #10
9; CHECK-NEXT:    bx lr
10entry:
11  %result.i = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 4)
12  %result.i.3 = call i32 @llvm.fshr.i32(i32 %result.i, i32 %result.i, i32 6)
13  ret i32 %result.i.3
14}
15
16; rotl (rotr x, 4), 6 -> rotl x, 2 -> ror r0, r0, #30
17define i32 @test1_alt(i32 %x) nounwind readnone {
18; CHECK-LABEL: test1_alt:
19; CHECK:       @ %bb.0: @ %entry
20; CHECK-NEXT:    ror r0, r0, #30
21; CHECK-NEXT:    bx lr
22entry:
23  %result.i = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 4)
24  %result.i.3 = call i32 @llvm.fshl.i32(i32 %result.i, i32 %result.i, i32 6)
25  ret i32 %result.i.3
26}
27
28; the same vector tests
29define <2 x i32> @test2(<2 x i32> %x) nounwind readnone {
30; CHECK-LABEL: test2:
31; CHECK:       @ %bb.0: @ %entry
32; CHECK-NEXT:    ror r0, r0, #10
33; CHECK-NEXT:    ror r1, r1, #10
34; CHECK-NEXT:    bx lr
35entry:
36  %result.i = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %x, <2 x i32> <i32 4, i32 4>)
37  %result.i.3 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %result.i, <2 x i32> %result.i, <2 x i32> <i32 6, i32 6>)
38  ret <2 x i32> %result.i.3
39}
40
41define <2 x i32> @test2_alt(<2 x i32> %x) nounwind readnone {
42; CHECK-LABEL: test2_alt:
43; CHECK:       @ %bb.0: @ %entry
44; CHECK-NEXT:    ror r0, r0, #30
45; CHECK-NEXT:    ror r1, r1, #30
46; CHECK-NEXT:    bx lr
47entry:
48  %result.i = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %x, <2 x i32> <i32 4, i32 4>)
49  %result.i.3 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %result.i, <2 x i32> %result.i, <2 x i32> <i32 6, i32 6>)
50  ret <2 x i32> %result.i.3
51}
52
53declare i32 @llvm.fshl.i32(i32, i32, i32)
54declare i32 @llvm.fshr.i32(i32, i32, i32)
55
56declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
57declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
58