1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-ARM 3; RUN: llc -mtriple=thumbv6m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V6 4; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V7 5 6define i32 @test1(i32 %X) nounwind { 7; CHECK-LABEL: test1: 8; CHECK: @ %bb.0: 9; CHECK-NEXT: rev16 r0, r0 10; CHECK-NEXT: bx lr 11 %tmp1 = lshr i32 %X, 8 12 %X15 = bitcast i32 %X to i32 13 %tmp4 = shl i32 %X15, 8 14 %tmp2 = and i32 %tmp1, 16711680 15 %tmp5 = and i32 %tmp4, -16777216 16 %tmp9 = and i32 %tmp1, 255 17 %tmp13 = and i32 %tmp4, 65280 18 %tmp6 = or i32 %tmp5, %tmp2 19 %tmp10 = or i32 %tmp6, %tmp13 20 %tmp14 = or i32 %tmp10, %tmp9 21 ret i32 %tmp14 22} 23 24define i32 @test2(i32 %X) nounwind { 25; CHECK-LABEL: test2: 26; CHECK: @ %bb.0: 27; CHECK-NEXT: revsh r0, r0 28; CHECK-NEXT: bx lr 29 %tmp1 = lshr i32 %X, 8 30 %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 31 %tmp3 = trunc i32 %X to i16 32 %tmp2 = and i16 %tmp1.upgrd.1, 255 33 %tmp4 = shl i16 %tmp3, 8 34 %tmp5 = or i16 %tmp2, %tmp4 35 %tmp5.upgrd.2 = sext i16 %tmp5 to i32 36 ret i32 %tmp5.upgrd.2 37} 38 39; rdar://9147637 40define i32 @test3(i16 zeroext %a) nounwind { 41; CHECK-LABEL: test3: 42; CHECK: @ %bb.0: @ %entry 43; CHECK-NEXT: revsh r0, r0 44; CHECK-NEXT: bx lr 45entry: 46 %0 = tail call i16 @llvm.bswap.i16(i16 %a) 47 %1 = sext i16 %0 to i32 48 ret i32 %1 49} 50 51declare i16 @llvm.bswap.i16(i16) nounwind readnone 52 53define i32 @test4(i16 zeroext %a) nounwind { 54; CHECK-LABEL: test4: 55; CHECK: @ %bb.0: @ %entry 56; CHECK-NEXT: revsh r0, r0 57; CHECK-NEXT: bx lr 58entry: 59 %conv = zext i16 %a to i32 60 %shr9 = lshr i16 %a, 8 61 %conv2 = zext i16 %shr9 to i32 62 %shl = shl nuw nsw i32 %conv, 8 63 %or = or i32 %conv2, %shl 64 %sext = shl i32 %or, 16 65 %conv8 = ashr exact i32 %sext, 16 66 ret i32 %conv8 67} 68 69; rdar://9609059 70define i32 @test5(i32 %i) nounwind readnone { 71; CHECK-ARM-LABEL: test5: 72; CHECK-ARM: @ %bb.0: @ %entry 73; CHECK-ARM-NEXT: revsh r0, r0 74; CHECK-ARM-NEXT: bx lr 75; 76; CHECK-V6-LABEL: test5: 77; CHECK-V6: @ %bb.0: @ %entry 78; CHECK-V6-NEXT: lsrs r1, r0, #8 79; CHECK-V6-NEXT: uxtb r1, r1 80; CHECK-V6-NEXT: lsls r0, r0, #24 81; CHECK-V6-NEXT: asrs r0, r0, #16 82; CHECK-V6-NEXT: adds r0, r0, r1 83; CHECK-V6-NEXT: bx lr 84; 85; CHECK-V7-LABEL: test5: 86; CHECK-V7: @ %bb.0: @ %entry 87; CHECK-V7-NEXT: revsh r0, r0 88; CHECK-V7-NEXT: bx lr 89entry: 90 %shl = shl i32 %i, 24 91 %shr = ashr exact i32 %shl, 16 92 %shr23 = lshr i32 %i, 8 93 %and = and i32 %shr23, 255 94 %or = or i32 %shr, %and 95 ret i32 %or 96} 97 98; rdar://9609108 99define i32 @test6(i32 %x) nounwind readnone { 100; CHECK-LABEL: test6: 101; CHECK: @ %bb.0: @ %entry 102; CHECK-NEXT: rev16 r0, r0 103; CHECK-NEXT: bx lr 104entry: 105 %and = shl i32 %x, 8 106 %shl = and i32 %and, 65280 107 %and2 = lshr i32 %x, 8 108 %shr11 = and i32 %and2, 255 109 %shr5 = and i32 %and2, 16711680 110 %shl9 = and i32 %and, -16777216 111 %or = or i32 %shr5, %shl9 112 %or6 = or i32 %or, %shr11 113 %or10 = or i32 %or6, %shl 114 ret i32 %or10 115} 116 117; rdar://9164521 118define i32 @test7(i32 %a) nounwind readnone { 119; CHECK-ARM-LABEL: test7: 120; CHECK-ARM: @ %bb.0: @ %entry 121; CHECK-ARM-NEXT: rev r0, r0 122; CHECK-ARM-NEXT: lsr r0, r0, #16 123; CHECK-ARM-NEXT: bx lr 124; 125; CHECK-V6-LABEL: test7: 126; CHECK-V6: @ %bb.0: @ %entry 127; CHECK-V6-NEXT: rev r0, r0 128; CHECK-V6-NEXT: lsrs r0, r0, #16 129; CHECK-V6-NEXT: bx lr 130; 131; CHECK-V7-LABEL: test7: 132; CHECK-V7: @ %bb.0: @ %entry 133; CHECK-V7-NEXT: rev r0, r0 134; CHECK-V7-NEXT: lsrs r0, r0, #16 135; CHECK-V7-NEXT: bx lr 136entry: 137 %and = lshr i32 %a, 8 138 %shr3 = and i32 %and, 255 139 %and2 = shl i32 %a, 8 140 %shl = and i32 %and2, 65280 141 %or = or i32 %shr3, %shl 142 ret i32 %or 143} 144 145define i32 @test8(i32 %a) nounwind readnone { 146; CHECK-LABEL: test8: 147; CHECK: @ %bb.0: @ %entry 148; CHECK-NEXT: revsh r0, r0 149; CHECK-NEXT: bx lr 150entry: 151 %and = lshr i32 %a, 8 152 %shr4 = and i32 %and, 255 153 %and2 = shl i32 %a, 8 154 %or = or i32 %shr4, %and2 155 %sext = shl i32 %or, 16 156 %conv3 = ashr exact i32 %sext, 16 157 ret i32 %conv3 158} 159 160; rdar://10750814 161define zeroext i16 @test9(i16 zeroext %v) nounwind readnone { 162; CHECK-LABEL: test9: 163; CHECK: @ %bb.0: @ %entry 164; CHECK-NEXT: rev16 r0, r0 165; CHECK-NEXT: bx lr 166entry: 167 %conv = zext i16 %v to i32 168 %shr4 = lshr i32 %conv, 8 169 %shl = shl nuw nsw i32 %conv, 8 170 %or = or i32 %shr4, %shl 171 %conv3 = trunc i32 %or to i16 172 ret i16 %conv3 173} 174 175define zeroext i16 @test10(i16 zeroext %v) nounwind readnone { 176; CHECK-LABEL: test10: 177; CHECK: @ %bb.0: @ %entry 178; CHECK-NEXT: rev16 r0, r0 179; CHECK-NEXT: bx lr 180entry: 181 %conv3 = call i16 @llvm.bswap.i16(i16 %v) 182 ret i16 %conv3 183} 184 185define i32 @pr55484(i32 %0) { 186; CHECK-ARM-LABEL: pr55484: 187; CHECK-ARM: @ %bb.0: 188; CHECK-ARM-NEXT: lsr r1, r0, #8 189; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #8 190; CHECK-ARM-NEXT: sxth r0, r0 191; CHECK-ARM-NEXT: bx lr 192; 193; CHECK-V6-LABEL: pr55484: 194; CHECK-V6: @ %bb.0: 195; CHECK-V6-NEXT: lsls r1, r0, #8 196; CHECK-V6-NEXT: lsrs r0, r0, #8 197; CHECK-V6-NEXT: orrs r0, r1 198; CHECK-V6-NEXT: sxth r0, r0 199; CHECK-V6-NEXT: bx lr 200; 201; CHECK-V7-LABEL: pr55484: 202; CHECK-V7: @ %bb.0: 203; CHECK-V7-NEXT: lsrs r1, r0, #8 204; CHECK-V7-NEXT: orr.w r0, r1, r0, lsl #8 205; CHECK-V7-NEXT: sxth r0, r0 206; CHECK-V7-NEXT: bx lr 207 %2 = lshr i32 %0, 8 208 %3 = shl i32 %0, 8 209 %4 = or i32 %2, %3 210 %5 = trunc i32 %4 to i16 211 %6 = sext i16 %5 to i32 212 ret i32 %6 213} 214