1; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s 2; RUN: llc -mtriple=thumbv7-none-linux-gnueabi < %s | FileCheck %s 3; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=-perfmon < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON 4; RUN: llc -mtriple=armv7m-none-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON 5; RUN: llc -mtriple=armv6-none-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON 6 7; The performance monitor we're looking for is an ARMv7 extension. It should be 8; possible to disable it, but realistically present on at least every v7-A 9; processor (but not on v6, at least by default). 10 11declare i64 @llvm.readcyclecounter() 12 13define i64 @get_count() { 14 %val = call i64 @llvm.readcyclecounter() 15 ret i64 %val 16 17 ; As usual, exact registers only sort of matter but the cycle-count had better 18 ; end up in r0 in the end. 19 20; CHECK: mrc p15, #0, r0, c9, c13, #0 21; CHECK: {{movs?}} r1, #0 22 23; CHECK-NO-PERFMON: {{movs?}} r0, #0 24; CHECK-NO-PERFMON: {{movs?}} r1, #0 25} 26